A SerDes can host multiple PCS links: QSGMII binds four ports to one
SerDes, USXGMII variants up to eight. Today pcs-handle references the
SerDes as a whole, with no way to express which link inside the SerDes
a port wants. The driver gets away with this because it carries its own
port->link bookkeeping and the link slot is implicit in DSA's port
iteration order -- functional, but the wiring information lives nowhere
in DT.
The upcoming fwnode_pcs migration moves PCS lookup to the generic
fwnode provider API, which disambiguates multiple instances per fwnode
via phandle cells. To make that landable as small, code-only commits,
the DT needs to carry the link index ahead of time.
Bump #pcs-cells from 0 to 1 on every SerDes node in the four SoC DTSIs
and append the link cell to every pcs-handle reference across boards
and the SWITCH_PORT_* macros. Cell values match the existing wiring:
0 for single-link SerDes (10GBase-R, SGMII, fiber, single-link
USXGMII), 0..3 per SerDes for QSGMII and USXGMII-QX, 0..7 for the
RTL9311 octal USXGMII layout.
No code reads the new cell yet -- of_parse_phandle_with_args() in the
PCS driver already cooperates with cells = 0 or 1, and the DSA glue
uses of_parse_phandle() which ignores cells entirely. The change is
runtime-neutral on its own; it exists so the follow-up code patches
can be a few lines each instead of dragging a bridge counter into the
driver to invent slot numbers DT could have provided directly.
Link: https://github.com/openwrt/openwrt/pull/23539
Signed-off-by: Jonas Jelonek <jelonek.jonas@gmail.com>
The RTL839x actually has two mdio busses.
- mdio bus 0 serves ports 0..23
- mdio bus 1 serves ports 24..51
This is baked into hardware and cannot be changed during mdio driver
setup with any register write. With the recent changes the driver
handles ports, phys and busses in a more logical way. So a port X
is assigned to a bus Y and a phy Z (on that bus). This gives a
mapping like
- port 16 <=> bus 0, address 16
- port 32 <=> bus 1, address 8
This unique assignment is used in the mdio driver as follows:
- Request to read bus 1, address 8
- Lookup corresponding port = 32
- Read from port 32
Looking at RTL839x it becomes clear that bus/phy => port lookup can
be achieved in multiple different ways. The simple reason is, that
for this device the driver cannot setup the smi topology. It is
baked into the hardware. So adding a "virtual" second bus does not
change the hardware access but allows to keep phy addresses below 32.
Making an example
mdio_bus0 {
PHY_C22(40, 40)
}
resolves to port 40. But the same can be achieved with
mdio_bus1 {
PHY_C22(40, 16)
}
In the first case the kernel sees bus/phy = 0/40 and in the second
case it sees bus/phy = 1/16. Both result in the access to the same
phy device on hardware port 40.
Use this analogy for RTL839x devices to match the real hardware
topology. For this change the existing dts and
- activate mdio bus 1 in rtl839x.dtsi
- rearrange devices with ports 24..51 to make use of bus 1
Signed-off-by: Markus Stockhausen <markus.stockhausen@gmx.de>
Link: https://github.com/openwrt/openwrt/pull/23186
Signed-off-by: Robert Marko <robimarko@gmail.com>
The Realtek target currently uses two phy macros to simplify the
device dts.
- EXTERNAL_PHY() to denote a phy attached to the SoC
- INTERNAL_PHY() to denote an internal PHY (inside the SoC)
There is no benefit doing this. The topology around a port/phy is
well defined by the port macros. They link port, phy, pcs and even
leds. The only consumer of the attribute "phy-is-integrated" is
inside the dsa driver and that is being refactored.
As a first step define a new more meaningful PHY_C22() macro that
describes a c22 capable phy. This does not need to care about the
external/internal relation. To make it even more useful for the
RTL93xx targets with multiple mdio busses give it two parameters
PHY_C22(port_number, bus_address) where
- port_number is the absolute overall unique phy number
- bus_address is the location of the phy on the bus
For RTL83xx these two parameters will usually be the same. Instead
of three steps (inventing the macro, converting the consumers and
removeing the old macor) do a one-step conversion for the existing
EXTERNAL_PHY() macro.
Signed-off-by: Markus Stockhausen <markus.stockhausen@gmx.de>
Link: https://github.com/openwrt/openwrt/pull/22698
Signed-off-by: Robert Marko <robimarko@gmail.com>
In most drivers upstream use "ethernet-ports" instead of "ports"
in dts. Especially the upstream rtl9300 mdio driver uses this to
lookup the port/phy mapping. Do the same downstream. There is no
need to adapt the dsa driver because it scans the dts via
for_each_node_by_name(dn, "port").
Signed-off-by: Markus Stockhausen <markus.stockhausen@gmx.de>
Link: https://github.com/openwrt/openwrt/pull/22149
Signed-off-by: Hauke Mehrtens <hauke@hauke-m.de>
The MAC addresses for eth0 and the individual LAN ports are now
configured via device tree. The assignment itself stays the same as
before, matching factory firmware.
The 02_network script still sets the bridge MAC address, as it is
different from the lowest port MAC address.
Signed-off-by: Jan Hoffmann <jan@3e8.eu>
Link: https://github.com/openwrt/openwrt/pull/21976
Signed-off-by: Robert Marko <robimarko@gmail.com>
Add the SerDes setup hooks in the PCS driver for RTL839x so that
pcs_config actually triggers configuration. Adjust the DTS of all
devices accordingly by adding pcs-handles and dropping phy-handles.
Signed-off-by: Jonas Jelonek <jelonek.jonas@gmail.com>
Link: https://github.com/openwrt/openwrt/pull/21360
Signed-off-by: Stijn Tintel <stijn@linux-ipv6.be>
The mdio controller got its own dts node with a dedicated bus node.
Until now it still searches the phy nodes in the ethernet node.
Change the driver so it searches the nodes at the right location.
For this to work move the phy nodes in all dts/dtsi over to the new
bus node. Use the following replacement rule:
Replace old full declaration
ðernet0 {
mdio-bus {
...
};
};
and old abbreviated declaration
&mdio {
...
};
simply with the new declaration
&mdio_bus0 {
...
};
Signed-off-by: Markus Stockhausen <markus.stockhausen@gmx.de>
Link: https://github.com/openwrt/openwrt/pull/19986
Signed-off-by: Hauke Mehrtens <hauke@hauke-m.de>
The 4 sfp ports on the RTL8214FC are actually wired to the gpio expander instead of internal.
Relatively minor changes to the dts are required, simply overriding some of the properties
inherited from rtl8393_hpe_1920.dtsi.
The speed is reported as 100/full and the media type is incorrect, but the ports pass traffic
just fine.
Signed-off-by: Joe Holden <jwh@zorins.us>
Link: https://github.com/openwrt/openwrt/pull/18914
Signed-off-by: Robert Marko <robimarko@gmail.com>
Some devices have both the color/function and label property defined.
The label can be constructed from the former properties, making it
redundant.
Signed-off-by: Sander Vanheule <sander@svanheule.net>
Hardware information:
---------------------
- SoC: RTL8393M
- Copper phy: 6×RTL8218B
- Fibre phy: RTL8214FC
- Flash: 32MiB SPI NOR, MX25L25635FMI
- RAM: 128MiB DDR3, Micron MT41K64M16TW-107
- Serial port: ±5V serial port to RJ45, ZT3232 (MAX3232 compatible)
- +370W POE on JG928A model
Note: SFP ports currently non-functional due to missing support for
RTL8214FC on the RTL8393M target.
Updated for Linux 6.6 kernel.
Installation:
-------------
- Initial installation follows same process as HPE 1920-24G (JG924A)
- Based on prior work of Jan Hoffmann <jan@3e8.eu>
- Additional work by Andreas Böhler <dev@aboehler.at>
- PoE updates and tidy-up by Stephen Howell <howels@allthatwemight.be>
Signed-off-by: Stephen Howell <howels@allthatwemight.be>
