The kernel config accidentally contains CONFIG_UBIFS_FS_AUTHENTICATION
which select a number of other unnecessary components, remove them.
The target has at least two subtargets, only one is currently
implemented. Move the Device builds into a file for this subtarget.
Signed-off-by: Caleb James DeLisle <cjd@cjdns.fr>
Link: https://github.com/openwrt/openwrt/pull/20027
Signed-off-by: Hauke Mehrtens <hauke@hauke-m.de>
Now that HSGMII is not used any longer drop the patch
the invents this mode.
Signed-off-by: Markus Stockhausen <markus.stockhausen@gmx.de>
Link: https://github.com/openwrt/openwrt/pull/20002
Signed-off-by: Hauke Mehrtens <hauke@hauke-m.de>
The only consumers of the Realtek HSGMII (2.5G SGMII) mode were
the RTL8226/RTL8221B PHYs. These have been converted to dynamic
SGMII/2500base-x mode switching. Drop the leftovers of the mode
implementation.
Signed-off-by: Markus Stockhausen <markus.stockhausen@gmx.de>
Link: https://github.com/openwrt/openwrt/pull/20002
Signed-off-by: Hauke Mehrtens <hauke@hauke-m.de>
The mdio controller got its own dts node with a dedicated bus node.
Until now it still searches the phy nodes in the ethernet node.
Change the driver so it searches the nodes at the right location.
For this to work move the phy nodes in all dts/dtsi over to the new
bus node. Use the following replacement rule:
Replace old full declaration
ðernet0 {
mdio-bus {
...
};
};
and old abbreviated declaration
&mdio {
...
};
simply with the new declaration
&mdio_bus0 {
...
};
Signed-off-by: Markus Stockhausen <markus.stockhausen@gmx.de>
Link: https://github.com/openwrt/openwrt/pull/19986
Signed-off-by: Hauke Mehrtens <hauke@hauke-m.de>
The mdio controller has now its own target specific device nodes. This
is much closer to upstream notation. Adapt the driver to make use of it.
Signed-off-by: Markus Stockhausen <markus.stockhausen@gmx.de>
Link: https://github.com/openwrt/openwrt/pull/19986
Signed-off-by: Hauke Mehrtens <hauke@hauke-m.de>
Until now the mdio bus is a subnode of the ethernet device. This
coupling is different from upstream and wrong. Ethernet and mdio
are different devices. Additionally differentiate between mdio
controller and mdio bus. To make it clear:
- There is one mdio controller
- With up to 4 busses (on RTL93xx)
Prepare new mdio controller and bus nodes with SoC specific compatibles.
These will be used later when refactoring the mdio driver probing.
Remark! For now only define the first bus for the RTL93xx targets.
So the driver still relies on "rtl9300,smi-address = <x y>;". It will
need much more refactoring to get totally aligned with upstream.
Signed-off-by: Markus Stockhausen <markus.stockhausen@gmx.de>
Link: https://github.com/openwrt/openwrt/pull/19986
Signed-off-by: Hauke Mehrtens <hauke@hauke-m.de>
While converting the RTL931x SerDes code to the new frontend
access methods, the target specific workarounds where left in
place. The old functions were kept and the phy/sds mapping
was unchanged too. It is time to clean this up
- drop the old functions
- reuse the existing read/write logic
- harden the new functions
For now keep the function naming rtmdio_...__new() as is. This
will be changed in a future commit.
Signed-off-by: Markus Stockhausen <markus.stockhausen@gmx.de>
Link: https://github.com/openwrt/openwrt/pull/19973
Signed-off-by: Hauke Mehrtens <hauke@hauke-m.de>
They have the same 0x200 calibration size.
Added various compatible lines in various places to make it clear what
device we're talking about.
Signed-off-by: Rosen Penev <rosenp@gmail.com>
Link: https://github.com/openwrt/openwrt/pull/19863
Signed-off-by: Hauke Mehrtens <hauke@hauke-m.de>
These devices use AR9285, which uses 1f8 as the calibration size, not
440 like newer chips do. Actually the driver mandates a minimum of 200.
Signed-off-by: Rosen Penev <rosenp@gmail.com>
Link: https://github.com/openwrt/openwrt/pull/19863
Signed-off-by: Hauke Mehrtens <hauke@hauke-m.de>
The TP-Link Archer VR1200v (v2) is a low end DSL modem based on the
EcoNet EN751221 processor platform.
While it does have an unlocked bootloader, the factory upgrade feature
requires a cryptographic signature so flashing from the web UI is not
feasible.
The Archer VR1200v (v2) uses a dual-image layout. I have chosen to reuse
this to support dual-boot between OpenWRT and the factory firmware.
Flashing instructions (from bootloader):
Build and then locate the squashfs-sysupgrade.bin image file
Get the length of that file in hex: printf '%X\n' "$(stat -c%s the-file-squashfs-sysupgrade.bin)"
Connect to device with xmodem capability, e.g. picocom --send-cmd lsx -vv -b 115200 /dev/ttyUSB0
Switch device on and press a key within 3 seconds, you should get to a `bldr>` prompt
Type: xmdm 80020000 <file length hex>
Quickly start xmodem and send the file, in picocom that is ctrl+a ctrl+s <paste-the-file-name> enter If the transfer fails to start, wait 30 seconds to a minute for the bootloader prompt to return and then try the command again.
Once the transfer has completed successfully, type the following flash 80000 80020000 <file length hex>
Type `re` or simply restart the device to boot into OpenWRT
Signed-off-by: Caleb James DeLisle <cjd@cjdns.fr>
Link: https://github.com/openwrt/openwrt/pull/19021
Signed-off-by: Hauke Mehrtens <hauke@hauke-m.de>
The SmartFiber XP8421-B is a fiber modem which is available for $20 online
and has 512MB of memory, 256MB of SPI NAND flash and 2 USB 2.0 ports in
addition to ethernet, wifi and XPON.
Because EcoNet is not currently producing evaluation boards, the XP8421-B
stands in as a convenient, low cost, off-the-shelf, representitive example
of the capabilities of the EN751221 econet processor. This is also the
example board that is included in the upstream Linux patchset.
The XP8421-B, and apparently many other devices of this platform, use a
dual-image layout. I have chosen to reuse this to support dual-boot between
OpenWRT and the factory firmware. Certain design decisions were made with
the goal of not overwriting data that is used by the factory OS.
This commit also introduces a utility for switching between OS_A and OS_B
which are used for OpenWRT and Factory OS respectively.
Flashing instructions (from bootloader):
Build and then locate the squashfs-tclinux.trx image file
Get the length of that file in hex: printf '%X\n' "$(stat -c%s the-file-squashfs-tclinux.trx)"
Connect to device with xmodem capability, e.g. picocom --send-cmd lsx -vv -b 115200 /dev/ttyUSB0
Switch device on and press a key within 3 seconds
Enter bootloader username and password: telecomadmin nE7jA%5m
Type: xmdm 80020000 <file length hex>
Quickly start xmodem and send the file, in picocom that is ctrl+a ctrl+s <paste-the-file-name> enter If the transfer fails to start, wait 30 seconds to a
minute for the bootloader prompt to return and then try the command again.
Once the transfer has completed successfully, type the following flash 80000 80020000 <file length hex>
Type go or simply restart the device to boot into OpenWRT
Signed-off-by: Caleb James DeLisle <cjd@cjdns.fr>
Link: https://github.com/openwrt/openwrt/pull/19021
Signed-off-by: Hauke Mehrtens <hauke@hauke-m.de>
EcoNet EN75xx is a big endian MIPS platform used in XPON (fiber),
DSL, and SIM (3g/4g) applications. Complete GPL vender SDKs exist
for this platform, but are based on Linux 2.6.
The bulk of this submission has already been accepted upstream:
https://patchwork.kernel.org/project/linux-mips/list/?series=960479&state=*
This platform uses a bootloader that is derived from old TrendChip
code. This bootloader implements a frustratingly complex Bad Block
Table which is implemented here in en75_bmt.c
This BMT is not upstreamed because it depends on mtk_bmt framework
which likewise is not upstreamed.
This BMT system rewrites block indexes in flash and if the bootloader
considers it to be corrupted, it will attempt to automatically rebuild
on boot. So without implementing the algorithm, you can't safely use
the disk at all.
Signed-off-by: Caleb James DeLisle <cjd@cjdns.fr>
Link: https://github.com/openwrt/openwrt/pull/19021
Signed-off-by: Hauke Mehrtens <hauke@hauke-m.de>
Hardware
--------
RockChip RK3568 ARM64 (4 cores)
1/2GB LPDDR4 RAM
2x 2500 Base-T (PCIe, r8125b)
1 LED (Power)
1 Button (Reset)
Micro-SD Slot
2x USB 3.0 Port
12V DC Jack
Installation
------------
Uncompress the OpenWrt sysupgrade and write it to a micro SD card using
dd.
Tested-by: Francisco G Luna <frangonlun@gmail.com>
Signed-off-by: Tianling Shen <cnsztl@immortalwrt.org>
Link: https://github.com/openwrt/openwrt/pull/19990
Signed-off-by: Hauke Mehrtens <hauke@hauke-m.de>
Add labels wan and cpu for ethernet ports.
Signed-off-by: Paweł Owoc <frut3k7@gmail.com>
Link: https://github.com/openwrt/openwrt/pull/19968
Signed-off-by: Hauke Mehrtens <hauke@hauke-m.de>
Currently 5G wireless interface MAC address is incorrect.
Fix by setting MAC address using Factory data.
Signed-off-by: Paweł Owoc <frut3k7@gmail.com>
Link: https://github.com/openwrt/openwrt/pull/19968
Signed-off-by: Hauke Mehrtens <hauke@hauke-m.de>
Convert NWA50AX Pro to use NVMEM framework for wifi macaddr.
Also remove the unused macaddr@a.
Signed-off-by: Zhi-Jun You <hujy652@protonmail.com>
Link: https://github.com/openwrt/openwrt/pull/19982
Signed-off-by: Hauke Mehrtens <hauke@hauke-m.de>
Convert NWA50AX Pro to use NVMEM framework for EEPROM/precal.
Signed-off-by: Zhi-Jun You <hujy652@protonmail.com>
Link: https://github.com/openwrt/openwrt/pull/19982
Signed-off-by: Hauke Mehrtens <hauke@hauke-m.de>
These are already specified in DTS. Only thing missing is
label-mac-device.
Signed-off-by: Rosen Penev <rosenp@gmail.com>
Link: https://github.com/openwrt/openwrt/pull/19806
Signed-off-by: Hauke Mehrtens <hauke@hauke-m.de>
Support in mt76 has existed for quite a while. Use it.
Signed-off-by: Rosen Penev <rosenp@gmail.com>
Link: https://github.com/openwrt/openwrt/pull/19806
Signed-off-by: Hauke Mehrtens <hauke@hauke-m.de>
After trying to implement the gluon support for this device I ended up in a boot loop due to the usable amount of flash left. With this patch layout it uses the unused and empty flash space in the original partiton layout.
The version 3 of this device the RE365 share the same approach to have more usable space.
Signed-off-by: Steffen Förster <nemesis@chemnitz.freifunk.net>
Link: https://github.com/openwrt/openwrt/pull/18639
Signed-off-by: Sander Vanheule <sander@svanheule.net>
A lot of definitions in the global mach include have been taken over
to the individual drivers. Only a few of the definitions are really
used nowadays. Remove all the unneeded lines.
Signed-off-by: Markus Stockhausen <markus.stockhausen@gmx.de>
Link: https://github.com/openwrt/openwrt/pull/19995
Signed-off-by: Robert Marko <robimarko@gmail.com>
- shrink data structures
- avoid unnecessary divisions
- support GSO fraglist on tx
Reapply with fixed patch
Signed-off-by: Felix Fietkau <nbd@nbd.name>
Use Linux kernel version 6.12 by default for loongarch64 target.
Signed-off-by: Weijie Gao <hackpascal@gmail.com>
Link: https://github.com/openwrt/openwrt/pull/19980
Signed-off-by: Hauke Mehrtens <hauke@hauke-m.de>
Boards such as [1] and [2] add an extra Ethernet port to Raspberry Pi (CM)5.
These typically use Realtek PCIe or USB Ethernet NICs. Include kmod-r8169 and
kmod-usb-net-rtl8152 by default to make it easy to configure LAN/WAN ports
with these parts on Raspberry Pi 5.
Because CM5 can fit in the same carrier boards as CM4, also ensure that both
devices have the same Ethernet NIC kmods.
[1]: https://www.waveshare.com/wiki/CM5-DUAL-ETH-MINI
[2]: https://www.waveshare.com/wiki/PCIe_TO_Gigabit_ETH_Board_(C)
Signed-off-by: Elbert Mai <code@elbertmai.com>
Link: https://github.com/openwrt/openwrt/pull/19384
Signed-off-by: Hauke Mehrtens <hauke@hauke-m.de>
Certain boards have an at24(-compatible) EEPROM for storing various
parameters like MAC addresses. Enable support for this hardware across
the whole target.
Signed-off-by: Zoltan HERPAI <wigyori@uid0.hu>
Backport fixes for Airoha pinctrl driver for PHY LED and MDIO bus. This
fix a copy-paste error for PHY LED and a misconfiguration for MT7530
embedded Switch MDIO bus GPIO pin to permit usage of external PHYs.
Signed-off-by: Christian Marangi <ansuelsmth@gmail.com>
The RK356x/RK3588 SoCs support up to 10 serial ports.
Signed-off-by: Tianling Shen <cnsztl@immortalwrt.org>
Link: https://github.com/openwrt/openwrt/pull/19917
Signed-off-by: Hauke Mehrtens <hauke@hauke-m.de>
Apart from improved power consumption, this fixes the runtime errors
from the pmdomain driver (failed to set idle on domain '%s')
Backport four clk fixes while at it.
Signed-off-by: Tianling Shen <cnsztl@immortalwrt.org>
Link: https://github.com/openwrt/openwrt/pull/19925
Signed-off-by: Hauke Mehrtens <hauke@hauke-m.de>
All devices supported by the Zynq target have either a Realtek or Marvell
PHY. The Vitesse PHY was enabled when the target was created (2d45ad07fc).
It's not used here, so it's safe to disable it.
Ethernet PHYs used by individual devices are listed below.
Device PHY
AVNET ZedBoard Marvell 88E1518
Digilent Zybo Realtek RTL8211E
Digilent Zybo Z7 Realtek RTL8211E or RTL8211F
Xilinx ZC702 Marvell 88E1116R
Signed-off-by: Aleksander Jan Bajkowski <olek2@wp.pl>
Link: https://github.com/openwrt/openwrt/pull/19969
Signed-off-by: Hauke Mehrtens <hauke@hauke-m.de>
This was done by executing these command:
$ make kernel_oldconfig CONFIG_TARGET=platform
Signed-off-by: Aleksander Jan Bajkowski <olek2@wp.pl>
Link: https://github.com/openwrt/openwrt/pull/19969
Signed-off-by: Hauke Mehrtens <hauke@hauke-m.de>
The devices are basically identical. The RAX3000Me can be with
ddr3 RAM.
Signed-off-by: Mikhail Zhilkin <csharper2005@gmail.com>
Link: https://github.com/openwrt/openwrt/pull/19760
Signed-off-by: Hauke Mehrtens <hauke@hauke-m.de>
This commit adds ddr3 build for the ddr3 variant of the CMCC RAX3000Me
router.
Signed-off-by: Mikhail Zhilkin <csharper2005@gmail.com>
Link: https://github.com/openwrt/openwrt/pull/19760
Signed-off-by: Hauke Mehrtens <hauke@hauke-m.de>
Hardware
--------
MediaTek MT7981 WiSoC
512MB DDR4 RAM
128MB SPI-NAND
MediaTek MT7981 2x2 DBDC 802.11ax 2T2R (2.4 / 5)
4 LAN MediaTek MT7531 PHY
1 WAN RTL8221B-VB-CG 2.5Gbps PHY
UART: 115200 8N1 3.3V
USB2 Port
PoE on WAN Port
MAC:
LAN MAC: label mac
WAN MAC: label mac + 1
2.4G MAC: label mac
5G MAC: label mac + 1 with LA bit set
Gotchas:
WAN LED does not light up (might require further DTS tweaks)
PoE on WAN port was not tested
This commit is heavily based on WR3000H one, I've just ported DTS differences
from the official image to get USB support and proper LED mapping.
Installation
------------
[Untested as I've received and used a transitional image from Cudy]
1. Connect to the serial port as described in the "Hardware" section.
2. Power on the device + press reset pin. Keep pressing reset pin to enter the U-Boot shell.
3. Download the OpenWrt initramfs image. Place it on an TFTP server
connected to the Cudy LAN ports. Make sure the server is reachable at
192.168.1.88. Rename the image to "cudy3000p.bin"
4. Download and boot the OpenWrt initramfs image.
$ tftpboot 0x46000000 cudy3000s.bin; bootm 0x46000000
5. Transfer the OpenWrt sysupgrade image to the device using scp.
Install with sysupgrade.
Signed-off-by: Michal Halva <hedik01@gmail.com>
Link: https://github.com/openwrt/openwrt/pull/19636
Signed-off-by: Hauke Mehrtens <hauke@hauke-m.de>
The Radxa E52C is a compact network computer using the Rockchip RK3582
SoC.
- https://radxa.com/products/network-computer/e52c
Hardware
--------
- Dual Cortex-A76 and Quad Cortex-A55 CPU
- 5 TOPS NPU
- 2/4/8GB LPDDR4 RAM
- 16/32/64GB on-board eMMC
- microSD card slot
- 2x 2.5 Gigabit Ethernet ports
- USB 3.1 Gen1 Type-A HOST/OTG port
- USB Type-C debug port
- USB Type-C power port
Installation
------------
Uncompress the OpenWrt sysupgrade and write it to a micro SD card or
eMMC using dd.
Signed-off-by: FUKAUMI Naoki <naoki@radxa.com>
Link: https://github.com/openwrt/openwrt/pull/19867
Signed-off-by: Hauke Mehrtens <hauke@hauke-m.de>
The Radxa ROCK 5C (Lite) is a single board computer using the Rockchip
RK3588S2 (RK3582) SoC.
- https://radxa.com/products/rock5/5c
Hardware
--------
- Quad (Dual) Cortex-A76 and Quad Cortex-A55 CPU
- Mali-G610 MP4 GPU (5C only)
- 6 (5) TOPS NPU
- 1/2/4/8/16/32GB LPDDR4X RAM
- eMMC/SPI NOR flash connector
- microSD card slot
- Wi-Fi 6 (AIC8800D80, not yet supported)
- Gigabit Ethernet port with PoE (additional PoE HAT required)
- USB 3.1 Gen1 Type-A HOST/OTG port
- USB 3.1 Gen1 Type-A HOST port
- 2x USB 2.0 Type-A HOST ports
- FPC connector with PCIe 2.1 x1
- PWM fan connector
- 20x2 pin header
- USB Type-C power port
Installation
------------
Uncompress the OpenWrt sysupgrade and write it to a micro SD card or
eMMC using dd.
Signed-off-by: FUKAUMI Naoki <naoki@radxa.com>
Link: https://github.com/openwrt/openwrt/pull/19867
Signed-off-by: Hauke Mehrtens <hauke@hauke-m.de>
The Radxa ROCK 5 ITX(+) is a Mini-ITX form factor computer using the
Rockchip RK3588 SoC.
- https://radxa.com/products/rock5/5itx
- https://radxa.com/products/rock5/5itxp
Hardware
--------
- Quad Cortex-A76 and Quad Cortex-A55 CPU
- Mali-G610 MP4 GPU
- 6 TOPS NPU
- 4/8/16/24/32GB LPDDR5 RAM
- on-board eMMC
- 16MB SPI NOR flash
- microSD card slot
- 2x 2.5 Gigabit Ethernet ports with PoE (additional PoE module required)
- USB 3.1 Gen1 Type-C HOST/OTG port
- 4x USB 3.1 Gen1 Type-A HOST ports
- 2x USB 2.0 Type-A HOST ports
- M.2 M Key connector with PCIe 3.0 x2
- 4x SATA connectors (ITX only)
- 2nd M.2 M Key connector with PCIe 3.0 x2 (ITX+ only)
- M.2 E Key connector with PCIe 2.1 x1 and USB 2.0
- RTC battery socket for CR1220
- 4pin PWM fan connector
- Serial console pin header
- Front panel pin headers
- 24pin ATX power connector
- 5525 12V DC jack
Installation
------------
Uncompress the OpenWrt sysupgrade and write it to a micro SD card or
eMMC using dd.
Signed-off-by: FUKAUMI Naoki <naoki@radxa.com>
Link: https://github.com/openwrt/openwrt/pull/19867
Signed-off-by: Hauke Mehrtens <hauke@hauke-m.de>
The Radxa ROCK 5B+ is a single board computer using the Rockchip
RK3588 SoC.
- https://radxa.com/products/rock5/5bp
Hardware
--------
- Quad Cortex-A76 and Quad Cortex-A55 CPU
- Mali-G610 MP4 GPU
- 6 TOPS NPU
- 4/8/16/24/32GB LPDDR5 RAM
- 16/32/64/128/256GB on-board eMMC (optional)
- 16MB SPI NOR flash
- microSD card slot
- Wi-Fi 6 (Realtek RTW8852BE)
- 2.5 Gigabit Ethernet port with PoE (additional PoE HAT required)
- USB 3.1 Gen1 Type-C HOST/OTG port
- 2x USB 3.1 Gen1 Type-A HOST ports
- 2x USB 2.0 Type-A HOST ports
- 2x M.2 M Key connectors with PCIe 3.0 x2
- M.2 B Key connector
- SIM card slot
- RTC battery connector
- PWM fan connector
- 20x2 pin header
- USB Type-C power port
Installation
------------
Uncompress the OpenWrt sysupgrade and write it to a micro SD card or
eMMC using dd.
Signed-off-by: FUKAUMI Naoki <naoki@radxa.com>
Link: https://github.com/openwrt/openwrt/pull/19867
Signed-off-by: Hauke Mehrtens <hauke@hauke-m.de>
Backport dts changes up to Linux v6.17 for Radxa E52C.
Signed-off-by: FUKAUMI Naoki <naoki@radxa.com>
Link: https://github.com/openwrt/openwrt/pull/19867
Signed-off-by: Hauke Mehrtens <hauke@hauke-m.de>
Backport dts changes up to Linux v6.17 for Radxa ROCK 5C and 5C Lite.
Signed-off-by: FUKAUMI Naoki <naoki@radxa.com>
Link: https://github.com/openwrt/openwrt/pull/19867
Signed-off-by: Hauke Mehrtens <hauke@hauke-m.de>
Backport dts changes up to Linux v6.17 for Radxa ROCK 5 ITX and ITX+.
Signed-off-by: FUKAUMI Naoki <naoki@radxa.com>
Link: https://github.com/openwrt/openwrt/pull/19867
Signed-off-by: Hauke Mehrtens <hauke@hauke-m.de>
Backport dts changes up to Linux v6.17 for Radxa ROCK 5B, 5B+, and 5T.
Signed-off-by: FUKAUMI Naoki <naoki@radxa.com>
Link: https://github.com/openwrt/openwrt/pull/19867
Signed-off-by: Hauke Mehrtens <hauke@hauke-m.de>
Backport dts changes up to Linux v6.17 for Radxa ROCK 5A.
Use power(green) LED instead of heartbeat(blue) LED.
Signed-off-by: FUKAUMI Naoki <naoki@radxa.com>
Link: https://github.com/openwrt/openwrt/pull/19867
Signed-off-by: Hauke Mehrtens <hauke@hauke-m.de>
Backport dts changes up to Linux v6.17 for Rockchip RK358x.
Signed-off-by: FUKAUMI Naoki <naoki@radxa.com>
Link: https://github.com/openwrt/openwrt/pull/19867
Signed-off-by: Hauke Mehrtens <hauke@hauke-m.de>
Backport gated-fixed-clk driver from Linux v6.13.
This is needed to fix a PCIe controller probe hang on the Radxa ROCK 5
ITX.
Signed-off-by: FUKAUMI Naoki <naoki@radxa.com>
Link: https://github.com/openwrt/openwrt/pull/19867
Signed-off-by: Hauke Mehrtens <hauke@hauke-m.de>
So much code was distributed between phy/ethernet/dsa drivers. A lot
was already cleand up before. With this step the mdio bus gets its
own space and is no longer hidden inside the ethernet driver.
This commit is mostly a copy/paste that includes only minor changes.
- define prefixes are renamed to RTMDIO
- The driver is totally self contained (does not rely on SoC include)
- The DTS structure (mdio node below ethernet node) was kept
- The driver is added to the kernel config of all subtargets.
Signed-off-by: Markus Stockhausen <markus.stockhausen@gmx.de>
Link: https://github.com/openwrt/openwrt/pull/19942
Signed-off-by: Robert Marko <robimarko@gmail.com>
The ethernet and mdio code will be splitted. The dsa driver depends
on proper loading of both, before switch setup can start. Sadly there
are severe cleanup issues in the probe() function if one of the
required devices is not available.
As a temporary workaround provide a dedicated check function that
verifies if the ethernet platform device driver is loaded and can
be used.
Signed-off-by: Markus Stockhausen <markus.stockhausen@gmx.de>
Link: https://github.com/openwrt/openwrt/pull/19942
Signed-off-by: Robert Marko <robimarko@gmail.com>
Use Unix LF style instead of Windows CRLF style.
Signed-off-by: Shiji Yang <yangshiji66@outlook.com>
Link: https://github.com/openwrt/openwrt/pull/19963
Signed-off-by: Robert Marko <robimarko@gmail.com>
At the end of RX NAPI polling the counter and mask registers are
cleaned up. Although this might run in parallel there is no
synchronization and the register modifications are some wild mix.
RTL83xx enables only the interrupt of a single ring while RTL93xx
just reactivates all interrupts (even for other NAPI threads).
Make use of the driver lock and only modify the interrupt bits that
the current thread owns.
Signed-off-by: Markus Stockhausen <markus.stockhausen@gmx.de>
Link: https://github.com/openwrt/openwrt/pull/19960
Signed-off-by: Robert Marko <robimarko@gmail.com>
Now that the counter registers work fine there is no need to
free buffers in software. Hardware will automatically block
input processing when software processing is too slow.
Signed-off-by: Markus Stockhausen <markus.stockhausen@gmx.de>
Link: https://github.com/openwrt/openwrt/pull/19960
Signed-off-by: Robert Marko <robimarko@gmail.com>
The receive path of the RTL93xx SoCs is currently discarding packets
in software. Analysis gives the following explanation:
- RX ring size registers are setup with the full software ring size
- When packets are received the packet counter registers are increased
- After RX processing the counter registers are changed the wrong way
- From then SOC is allowed to receive more packets than software allows
- Overflow interrupts are fired
- As a reaction to that the software drops packets
Change the processing as follows:
- Setup ring size registers with a headroom of 2 buffers
- Decrease the counter registers with the real work done
With this change no more overflow interrupts occur because the SoC
disables the queues before they can overflow or hit a buffer that is
still owned by the CPU.
Benchmark from single stream iperf3 run, with server process running
on ZyXEL XGS1210 (RTL930x).
iperf3 run before
-----------------------------------------------------------
Server listening on 5201 (test #1)
-----------------------------------------------------------
Accepted connection from 192.168.2.86, port 54412
[ 5] local 192.168.2.71 port 5201 connected to 192.168.2.86 port 54418
[ ID] Interval Transfer Bitrate
[ 5] 0.00-1.00 sec 384 KBytes 3.14 Mbits/sec
[ 5] 1.00-2.00 sec 0.00 Bytes 0.00 bits/sec
[ 5] 2.00-3.00 sec 0.00 Bytes 0.00 bits/sec
[ 5] 3.00-4.01 sec 5.12 MBytes 42.8 Mbits/sec
[ 5] 4.01-5.00 sec 11.4 MBytes 95.8 Mbits/sec
[ 5] 5.00-6.00 sec 0.00 Bytes 0.00 bits/sec
[ 5] 6.00-7.00 sec 0.00 Bytes 0.00 bits/sec
[ 5] 7.00-8.00 sec 0.00 Bytes 0.00 bits/sec
[ 5] 8.00-9.00 sec 0.00 Bytes 0.00 bits/sec
[ 5] 9.00-10.00 sec 0.00 Bytes 0.00 bits/sec
iperf3 run after
-----------------------------------------------------------
Server listening on 5201 (test #1)
-----------------------------------------------------------
Accepted connection from 192.168.2.86, port 55228
[ 5] local 192.168.2.71 port 5201 connected to 192.168.2.86 port 55232
[ ID] Interval Transfer Bitrate
[ 5] 0.00-1.00 sec 22.8 MBytes 191 Mbits/sec
[ 5] 1.00-2.01 sec 25.4 MBytes 211 Mbits/sec
[ 5] 2.01-3.00 sec 25.4 MBytes 215 Mbits/sec
[ 5] 3.00-4.01 sec 26.5 MBytes 220 Mbits/sec
[ 5] 4.01-5.00 sec 26.2 MBytes 222 Mbits/sec
[ 5] 5.00-6.00 sec 26.9 MBytes 225 Mbits/sec
[ 5] 6.00-7.00 sec 27.0 MBytes 226 Mbits/sec
[ 5] 7.00-8.01 sec 26.9 MBytes 224 Mbits/sec
[ 5] 8.01-9.00 sec 26.5 MBytes 223 Mbits/sec
[ 5] 9.00-10.00 sec 26.8 MBytes 225 Mbits/sec
[ 5] 10.00-10.02 sec 640 KBytes 224 Mbits/sec
Signed-off-by: Markus Stockhausen <markus.stockhausen@gmx.de>
Link: https://github.com/openwrt/openwrt/pull/19960
Signed-off-by: Robert Marko <robimarko@gmail.com>
Backport quirks for two SFP+ modules. Both support the RollBall protocol.
The fix for the FLYPRO module is queued in net-next tree.
Signed-off-by: Aleksander Jan Bajkowski <olek2@wp.pl>
Link: https://github.com/openwrt/openwrt/pull/19949
Signed-off-by: Hauke Mehrtens <hauke@hauke-m.de>
These patches hacked the set_eee() and get_eee() functions into
the phy_driver. Drop them with no consumer left.
Signed-off-by: Markus Stockhausen <markus.stockhausen@gmx.de>
Link: https://github.com/openwrt/openwrt/pull/19906
Signed-off-by: Hauke Mehrtens <hauke@hauke-m.de>
Since we are using upstream PHY drivers there is no more need
for the downstream version. Side effect is that the SoC dependent
polling functions are no longer needed. This was always wrong
in this driver.
Signed-off-by: Markus Stockhausen <markus.stockhausen@gmx.de>
Link: https://github.com/openwrt/openwrt/pull/19906
Signed-off-by: Hauke Mehrtens <hauke@hauke-m.de>
A new version of the ZyXEL XGS1210-12 has been discovered in
the wild. It includes at least two known hardware changes
- lan9/lan10 use RTL8221B instead of RTL8226
- lan9/lan10 use different SMI busses
Pave the new device the way by splitting the existing DTS.
According to the vendor website the models are named
- A1 (first version): not explicetly labeled
- B1 (second version): Label Rev. B1 on device
Rename the current OpenWrt device definition to A1 as it was
made for the first version. To stay compatible with older
installations, add the old device name to the list of
supported devices.
Signed-off-by: Markus Stockhausen <markus.stockhausen@gmx.de>
Link: https://github.com/openwrt/openwrt/pull/19908
Signed-off-by: Hauke Mehrtens <hauke@hauke-m.de>
The rt-loader currently only supports booting piggy backed lzma
compressed kernels. This requires a data layout where the kernel
directly follows the loader. That might not be sufficient for
more complex flash layouts.
Especially bootbase devices (like ZyXEL GS1920) will need some
kind of chain loading that needs to be explored yet.
Enhance the rt-loader as follows:
- Allow to build as standalone version
- In this case a flash start address is given
- During boot loader will search the ROM starting from that address
- If it finds a uImage this will be loaded into RAM
- Afterwards it will be decompressed to its load address
- While we are here add uncompressed uImage support
As always the implementation tries to be as simple as possible.
- uImage detection works without magics
- uImage will be loaded to highest possible memory address
- Documentation in Makefile has been adapted accordingly
Funny side fact: A standalone rt-loader can chain load a piggy
backed rt-loader from flash.
During bootup loader will show
rt-loader
Running on RTL8380M (chip id 6275C) with 256MB
Relocate 15760 bytes from 0x82000000 to 0x8ffa0000
Searching for uImage starting at 0xb45a0000 ...
uImage 'MIPS OpenWrt Linux-6.12.40' found at 0xb45a0000 with load address 0x80100000
Copy 2923034 bytes of image data to 0x8fcd61e6 ...
Extract image with 2923034 bytes from 0x8fcd61e6 to 0x80100000 ...
Final kernel size is 2923034 bytes
Booting kernel from 0x80100000 ...
Signed-off-by: Markus Stockhausen <markus.stockhausen@gmx.de>
Link: https://github.com/openwrt/openwrt/pull/19832
Signed-off-by: Hauke Mehrtens <hauke@hauke-m.de>
Provide a crc32 function (will be needed later). Do some
minor naming and coding cleanups
Signed-off-by: Markus Stockhausen <markus.stockhausen@gmx.de>
Link: https://github.com/openwrt/openwrt/pull/19832
Signed-off-by: Hauke Mehrtens <hauke@hauke-m.de>
Registers must not be accessed in parallel by multiple drivers.
Read-modify-write operations are not atomic, and the result of parallel
access is undefined.
The MAC_L2_GLOBAL_CTRL2 register is essentially a pin configuration
register and is represented by a pinmux node in the devicetree. Operations
on this register by the realtek,rtl838x-eth driver must therefore also be
reflected in the devicetree.
Since the MDIO sets used are board-specific, the pins must be enabled in
the board’s devicetree. This can be achieved using the pinctrl properties
for the realtek,rtl83xx-switch.
&switch0 {
pinctrl-names = "default";
pinctrl-0 = <&pinmux_enable_mdc_mdio_0>,
<&pinmux_enable_mdc_mdio_1>;
....
};
Signed-off-by: Sven Eckelmann <sven@narfation.org>
Link: https://github.com/openwrt/openwrt/pull/19815
Signed-off-by: Robert Marko <robimarko@gmail.com>
The pinmux-related registers on the RTL931X SoC family are spread across
various non-consecutive registers. It might be tempting to modify them
directly in a specific driver (SPI, LED, etc.), but this would cause issues
with parallel, non-locked read-modify-write operations, which are required
to update individual portions of these registers.
Instead, it is better to use the devicetree pinctrl properties to define
the correct configurations for the various operation modes.
One important setting here is the LED Sync bit. This allows the LED
controller to generate an additional positive edge on the `STCP`
("STore Clock Pin", also known as `RCLK`) of the LED shift register after
the actual content has already been shifted in using the normal shift
clock. The LED shift register is then expected to copy the content from the
shift register section into the storage registers, which act as the actual
LED output control. This functionality is available in, and commonly used
with, the SNx4HC595 family of shift registers.
To activate it, simply register it in the default state of the
"realtek,rtl83xx-switch" node:
&switch0 {
pinctrl-names = "default";
pinctrl-0 = <&pinmux_enable_led_sync>;
....
};
It would be nicer when this can be directly added to the led subnode. But
for this to work, `realtek,rtl9300-leds` must first be an actual driver
(known to the driver core).
[1] https://www.ti.com/lit/ds/symlink/sn74hc595.pdf
Suggested-by: Bevan Weiss <bevan.weiss@gmail.com>
Signed-off-by: Sven Eckelmann <sven@narfation.org>
Link: https://github.com/openwrt/openwrt/pull/19815
Signed-off-by: Robert Marko <robimarko@gmail.com>
The MAC_L2_GLOBAL_CTRL2 register is primarily used for pin configuration.
It is necessary to select specific modes for pins or to free them for use
as GPIOs.
Fixes: 9dbc04785c ("realtek: add rtl8231-aux to rtl931x.dtsi")
Signed-off-by: Sven Eckelmann <sven@narfation.org>
Link: https://github.com/openwrt/openwrt/pull/19815
Signed-off-by: Robert Marko <robimarko@gmail.com>
The pinmux-related registers on the RTL930X SoC family are spread across
various non-consecutive registers. It might be tempting to modify them
directly in a specific driver (SPI, LED, etc.), but this would cause issues
with parallel, non-locked read-modify-write operations, which are required
to update individual portions of these registers.
Instead, it is better to use the devicetree pinctrl properties to define
the correct configurations for the various operation modes.
One important setting here is the LED Sync bit. This allows the LED
controller to generate an additional positive edge on the `STCP`
("STore Clock Pin", also known as `RCLK`) of the LED shift register after
the actual content has already been shifted in using the normal shift
clock. The LED shift register is then expected to copy the content from the
shift register section into the storage registers, which act as the actual
LED output control. This functionality is available in, and commonly used
with, the SNx4HC595 family of shift registers.
To activate it, simply register it in the default state of the
"realtek,rtl83xx-switch" node:
&switch0 {
pinctrl-names = "default";
pinctrl-0 = <&pinmux_enable_led_sync>;
....
};
It would be nicer when this can be directly added to the led subnode. But
for this to work, `realtek,rtl9300-leds` must first be an actual driver
(known to the driver core).
[1] https://www.ti.com/lit/ds/symlink/sn74hc595.pdf
Suggested-by: Bevan Weiss <bevan.weiss@gmail.com>
Signed-off-by: Sven Eckelmann <sven@narfation.org>
Link: https://github.com/openwrt/openwrt/pull/19815
Signed-off-by: Robert Marko <robimarko@gmail.com>
Add the NPU and reserved memory node for AN7581 dtsi since it's not
supported.
Link: https://github.com/openwrt/openwrt/pull/19816
Signed-off-by: Christian Marangi <ansuelsmth@gmail.com>
Major backport of upstream patch for support of multiple feature of the
Airoha Ethernet driver.
Feature backported are TSO, Jumbo packet, Offload and initial Wlan
Offload support.
Link: https://github.com/openwrt/openwrt/pull/19816
Signed-off-by: Christian Marangi <ansuelsmth@gmail.com>
Backport trivial fixes from upstream related to pinctrl and ethernet
driver.
Link: https://github.com/openwrt/openwrt/pull/19816
Signed-off-by: Christian Marangi <ansuelsmth@gmail.com>
Backport patch adding support for AN7581 Ethernet PHY based on the same
Mediatek embedded Switch PHY.
Link: https://github.com/openwrt/openwrt/pull/19816
Signed-off-by: Christian Marangi <ansuelsmth@gmail.com>
Mediatek PHY patch has been merged upstream. Reintroduce them to
backport directory as the same PHY is also needed for Airoha target.
All the affected patch automatically refreshed.
Link: https://github.com/openwrt/openwrt/pull/19816
Signed-off-by: Christian Marangi <ansuelsmth@gmail.com>
Backport support for Aeonsemi AS121xxx PHY. The PHY require dedicated
firmware to be loaded to correctly work and support a big family of
Aeonsemi PHY that provide from 1G to 10G speed.
Automatically refresh all affected patch and file (rtl PHY).
Link: https://github.com/openwrt/openwrt/pull/19816
Signed-off-by: Christian Marangi <ansuelsmth@gmail.com>
Replace thermal patch with upstream version. The thermal maintainer
reported that the sysfs entry are considered deprecated and that slope
and offset should be handled internally to the driver.
Link: https://github.com/openwrt/openwrt/pull/19816
Signed-off-by: Christian Marangi <ansuelsmth@gmail.com>
Fix the model name in DTS compatible, Makefiles and board scripts by
using dash instead of comma or underscore. This aligns it with other
examples in OpenWrt and makes in consistent in all places where the
board model is used.
'tplink,tl-st1008f,v2' --> 'tplink,tl-st1008f-v2'
'tplink,tl-st1008f_v2' --> 'tplink,tl-st1008f-v2'
Fixes: 39b9b491bb ("realtek: add support for TP-Link TL-ST1008F v2.0")
Fixes: #19930
Signed-off-by: Jonas Jelonek <jelonek.jonas@gmail.com>
Link: https://github.com/openwrt/openwrt/pull/19934
Signed-off-by: Hauke Mehrtens <hauke@hauke-m.de>
Backport a patch from upstream kernel 6.17-rc4 which fixes a regression
introduced in the latest stable kernel versions.
This is already in the Linus stable queues for the next minor kernel
updates.
Fixes: 1c92e468d5 ("kernel: bump 6.6 to 6.6.103")
Fixes: f39c7e103f ("kernel: bump 6.12 to 6.12.43")
Reported-by: Goetz Goerisch <ggoerisch@gmail.com>
Signed-off-by: Hauke Mehrtens <hauke@hauke-m.de>
Currently the calculation for the CMU (even) SerDes works similar
to this pseudo code.
analog_backend_serdes = get_analog_serdes(frontend_serdes);
even_backend_serdes = analog_backend_serdes & ~1;
write_to(even_backend_serdes);
Because of the SerDes layout and frontend/backend mapping this can
be swapped to the following order with the same resulting Serdes.
even_frontend_serdes = frontend_serdes ~1;
analog_backend_serdes = get_analog_serdes(even_frontend_serdes);
write_to(analog_backed_serdes);
In the later example the frontend/backend mapping code is already
in our new functions. So swap the calculation logic and use the
new access functions. This allows to finally drop the old access
functions without mapping.
From now on all RTL931x SerDes functions will use a consistent
frontend view.
Signed-off-by: Markus Stockhausen <markus.stockhausen@gmx.de>
Link: https://github.com/openwrt/openwrt/pull/19873
Signed-off-by: Hauke Mehrtens <hauke@hauke-m.de>
The RTL931x has 14 frontend and at least 26 backend serdes. Currently
the programming functions always need to determine the right backend
serdes from the given frontend serdes on their own. We plan to provide
a consistent serdes mapping to all callers.
As the third step make use of these new functions whenever we want to
access the "digital 2" pages. The pages are mapped starting at 0x200.
So the function conversion is as simple as this:
Old:
dsds = (sds - 1) * 2;
rtmdio_931x_read_sds_phy(dsds + 1, page, ...)
New:
rtmdio_931x_read_sds_phy_new(sds, page + 0x200, ...)
Signed-off-by: Markus Stockhausen <markus.stockhausen@gmx.de>
Link: https://github.com/openwrt/openwrt/pull/19873
Signed-off-by: Hauke Mehrtens <hauke@hauke-m.de>
The more we step down into the SerDes deeps the more confusing it
gets. Nevertheless it is not to late to fix a wrong assumption.
Until now it seemed as if the frontend/backend SerDes mapping is
totally without intersection. This is not true.
The backend SerDes mapping is also dependent on the mode. Especially
the proprietary Realtek XSGMII mode stands out from all other
mappings. So fix the descriptions and the calculation of the third
page package (digital 2 aka XSGMII 2).
As it was not yet used it had no impact.
Fixes: a4cbb44c1b ("realtek: convert access to RTL931x analog serdes pages")
Signed-off-by: Markus Stockhausen <markus.stockhausen@gmx.de>
Link: https://github.com/openwrt/openwrt/pull/19873
Signed-off-by: Hauke Mehrtens <hauke@hauke-m.de>
The RTL931x has 14 frontend and at least 26 backend serdes. Currently
the programming functions always need to determine the right backend
serdes from the given frontend serdes on their own. We plan to provide
a consistent serdes mapping to all callers.
As the second step make use of these new functions whenever we
want to access the digital 1 pages. The pages are mapped starting
at 0x100. So the function conversion is as simple as this:
Old:
dsds = (sds - 1) * 2;
rtmdio_931x_read_sds_phy(dsds, page, ...)
New:
rtmdio_931x_read_sds_phy_new(sds, page + 0x100, ...)
Signed-off-by: Markus Stockhausen <markus.stockhausen@gmx.de>
Link: https://github.com/openwrt/openwrt/pull/19873
Signed-off-by: Hauke Mehrtens <hauke@hauke-m.de>
For some reason 3 of the 4 mdio access functions contain an
artifical delay of 10ms. While it might have been part of
older Realtek SDKs it can no longer be found in current ones.
Remove the delays.
While we are here remove the pre-access bus ready checks.
It is sufficient to run them after the command start. If
anything fails the caller will get an error. This is the
same behaviour as for the other targets.
Finally cleanup the error handling. Something like this makes
no sense at all.
err = rtmdio_838x_smi_wait_op(100000);
if (err)
goto errout;
err = 0;
errout:
Signed-off-by: Markus Stockhausen <markus.stockhausen@gmx.de>
Link: https://github.com/openwrt/openwrt/pull/19901
Signed-off-by: Robert Marko <robimarko@gmail.com>
When sending llc packets with vlan tx offload, the hardware fails to
actually add the tag. Deal with this by fixing it up in software.
Fixes: https://github.com/openwrt/openwrt/issues/19916
Reported-by: Thibaut VARENE <hacks@slashdirt.org>
Signed-off-by: Felix Fietkau <nbd@nbd.name>
Most drivers have this as const. Especially upstream in the kernel.
Signed-off-by: Rosen Penev <rosenp@gmail.com>
Link: https://github.com/openwrt/openwrt/pull/19911
Signed-off-by: Hauke Mehrtens <hauke@hauke-m.de>
Import upstream patches fixing issues with unreliable temperature
reading on some batches of the MediaTek MT7988 SoCs.
Signed-off-by: Daniel Golle <daniel@makrotopia.org>
Prepare the SerDes patch function to allow different patch sequences
depending on the phy mode. Patches are required to allow devices with a
lightweight bootloader (one that doesn't have a "rtk network init"
command) to use the serdes. Some modes required a different patch
sequence than the one currently used.
Signed-off-by: Damien Dejean <dam.dejean@gmail.com>
Link: https://github.com/openwrt/openwrt/pull/19834
Signed-off-by: Hauke Mehrtens <hauke@hauke-m.de>
The addition of the soft_reset() function to the RTL8221B PHYs
missed to take care of C22/C45 standalone PHY versions. Especially
on RTL930x switch devices with these PHY the reset fails for the
C45 operation mode. This comes from the fact that the mdio bus
disables C22 read/writes when being set to C45.
Upstream has gained a proper C45 reset function. Use it for the
C45 PHY models.
Fixes: 7e3284eef7 ("generic: use genphy_soft_reset for RealTek 2.5G PHYs")
Signed-off-by: Markus Stockhausen <markus.stockhausen@gmx.de>
Link: https://github.com/openwrt/openwrt/pull/19843
Signed-off-by: Hauke Mehrtens <hauke@hauke-m.de>
We reached the point of no return. Upstream has gained the final
bits for the RTL8226 PHYs. That means.
- RTL8226 MAC side behaves like RTL8221(B)
- It's serdes no longer uses proprietary HSGMII (2.5G SGMII)
- Instead it dynamically switches between SGMII and 2500base-x
This (partly) solves one of the central henn/egg problems of the
Realtek target. To change the MAC/PHY interface mode both sides
need to have all bits in place to do so. But where to start if
so much needs to be done?
Now the PHY side has created facts and it mitigates a lot of
problems. All downstream HSGMII patches and coding can be dropped
in the future.
For now only adapt the only DTS that still maps PHYs to HSGMII.
Signed-off-by: Markus Stockhausen <markus.stockhausen@gmx.de>
Link: https://github.com/openwrt/openwrt/pull/19843
Signed-off-by: Hauke Mehrtens <hauke@hauke-m.de>
The patching sequence of the RTL8214x/8218x is very similar.
Especially the preparation for readiness is always the same.
Provide a common helper to improve readability.
While we are here clean up the changed functions
- Sort variable definitions according to upstream
- simplify some messages
Signed-off-by: Markus Stockhausen <markus.stockhausen@gmx.de>
Link: https://github.com/openwrt/openwrt/pull/19810
Signed-off-by: Hauke Mehrtens <hauke@hauke-m.de>
Our phy driver can handle some multiport phys (e.g. RTL8218B
or RTL8214FC). To access arbitrary ports some package access
functions have been defined. These were implemented in the
mdio bus with poor knowledge about the phy/mdio dependencies.
So they add unneeded complexity to the bus and the phy driver
must access these external functions directly.
Provide a new helper get_package_phy() that can derive any
phy device in a package from a given phy of that package.
Make use of this local helper and cut the mdio dependency.
While we refactor several firmware patching functions rename
the loop variables to "port" to better indicate what we are
working on.
Signed-off-by: Markus Stockhausen <markus.stockhausen@gmx.de>
Link: https://github.com/openwrt/openwrt/pull/19810
Signed-off-by: Hauke Mehrtens <hauke@hauke-m.de>
Now that we have a get_base_phy() function a lot code of the RTL8214FC
handling can be cleaned up. To name a few:
- use phy_read/phy_write instead of mdiobus functions or the even worse
phy_package_..._paged() helpers
- replace messages with phydev_info()
- remove if/else statements around copper/fibre handling
Signed-off-by: Markus Stockhausen <markus.stockhausen@gmx.de>
Link: https://github.com/openwrt/openwrt/pull/19810
Signed-off-by: Hauke Mehrtens <hauke@hauke-m.de>
Currently phy packages (like RTL8214x/RTL8218x) are patched and
initialized as soon as the first phy of the package is found.
In this situation the shared structure is not finalized because
devm_phy_package_join() has only been called for the first phy.
This is no issue as the patching directly hammers the bus addresses
for the follow-up phys.
In the future we want to simplify the package handling and allow
to access all phy_device structures from only one phy_device of
the package. With this we can use normal phy_read/phy_write.
Switch the probing logic to "late patching". With this we will
initialize the firmware of the package when the last phy of the
package has been found and thus the shared structure is complete.
Provide get_base_phy() as the first package helper that allows
to determine the first phy of the package from any other phy.
While we are here drop the shared structure that only repeats the
phy name and has no other use.
Signed-off-by: Markus Stockhausen <markus.stockhausen@gmx.de>
Link: https://github.com/openwrt/openwrt/pull/19810
Signed-off-by: Hauke Mehrtens <hauke@hauke-m.de>
The Plasma Cloud PSX10 Switch is a 8 + 2 port multi-GBit switch with
8x 10/100/1000/2500BaseT Ethernet ports and 2x SFP+ module slot.
Hardware:
- RTL9302C SoC
- Macronix MX25L25645G (32MB flash)
- Winbond W632GU6NB-12 (256MB DDR3 SDRAM - only 128 MB configured*)
- 2x RTL8224 4x 10m/100m/1/2.5 Gigabit PHY
- SFP+ 2x 10GBit slot
- IC+ IP8008 POE+ PSE controller
The switch is powered by 54 Volts 2.77A barrel connector. The internal TTL
serial connector can be used to access the terminal. Pins from 1: TX RX
(unused) GND. Serial connection is via 115200 baud, 8N1.
A reset button is accessible through a hole in the front panel.
*) Only 128 MB of RAM are currently configured because there were
infrequent random memory corruptions detected when using memtester with a
256 MB DT configuration. This could also be reproduced with RTLSDK.
Installation
------------
* The device can be flashed by using sysupgrade command. Either from the
original vendor firmware or using an initramfs (see "Debug")
* Connect serial as per the layout above. Connection parameters: 115200 8N1
* The image must be copied using scp to /tmp of the device
scp openwrt-realtek-rtl930x-plasmacloud_psx10-squashfs-sysupgrade.bin root@[IP address of the device]:/tmp/
* start sysupgrade without saving the original vendor configuration
sysupgrade -n /tmp/openwrt-realtek-rtl930x-plasmacloud_psx10-squashfs-sysupgrade.bin
Installation via u-boot
-----------------------
If you have an TFTP server connected to the switch, it is possible to
directly install the device using the factory image from u-boot
# setup networking and IP of TFP server
rtk network on
setenv ipaddr 10.100.100.99
setenv serverip 10.100.100.20
# get factory image
tftp 0x84000000 factory.bin
# erase firmware partitions
sf probe 0
sf erase 0x100000 0x01f00000
# write firmware to both partitions
sf write ${fileaddr} 0x100000 ${filesize}
sf write ${fileaddr} 0x1080000 ${filesize}
# adjust the boot commands
setenv bootargs "mtdparts=spi0.0:896k(u-boot),64k(u-boot-env),64k(u-boot-env2),15872k(inactive),15872k(firmware2)"
setenv bootcmd "rtk init; bootm 0xb5080000"
# restart
reset
Debug
-----
* Connect serial as per the layout above. Connection parameters: 115200 8N1.
* A tftp server is required, tftpd-hpa works well.
* Power the device, at U-Boot start rapidly hit Esc key to stop autoboot
* Enable network:
rtk network on
* Change ip address of device:
setenv ipaddr 192.168.1.6
* Download initramfs from TFTP server:
tftpboot 0x84000000 192.168.1.111:openwrt-realtek-rtl930x-plasmacloud_psx10-initramfs-kernel.bin
* Boot loaded file:
bootm 0x84000000
Signed-off-by: Harshal Gohel <hg@simonwunderlich.de>
Co-developed-by: Sharadanand Karanjkar <sk@simonwunderlich.de>
Signed-off-by: Sharadanand Karanjkar <sk@simonwunderlich.de>
Link: https://github.com/openwrt/openwrt/pull/19362
Signed-off-by: Hauke Mehrtens <hauke@hauke-m.de>
The Plasma Cloud PSX8 Switch is a 8 port multi-GBit switch with
8x 10/100/1000/2500BaseT Ethernet ports.
Hardware:
- RTL9302C SoC
- Macronix MX25L25645G (32MB flash)
- Winbond W632GU6NB-12 (256MB DDR3 SDRAM - only 128 MB configured*)
- 2x RTL8224 4x 10m/100m/1/2.5 Gigabit PHY
- IC+ IP8008 POE+ PSE controller
The switch is powered by 54 Volts 2.77A barrel connector. The internal TTL
serial connector can be used to access the terminal. Pins from 1: TX RX
(unused) GND. Serial connection is via 115200 baud, 8N1.
A reset button is accessible through a hole in the front panel.
*) Only 128 MB of RAM are currently configured because there were
infrequent random memory corruptions detected when using memtester with a
256 MB DT configuration. This could also be reproduced with RTLSDK.
Installation
------------
* The device can be flashed by using sysupgrade command. Either from the
original vendor firmware or using an initramfs (see "Debug")
* Connect serial as per the layout above. Connection parameters: 115200 8N1
* The image must be copied using scp to /tmp of the device
scp openwrt-realtek-rtl930x-plasmacloud_psx8-squashfs-sysupgrade.bin root@[IP address of the device]:/tmp/
* start sysupgrade without saving the original vendor configuration
sysupgrade -n /tmp/openwrt-realtek-rtl930x-plasmacloud_psx8-squashfs-sysupgrade.bin
Installation via u-boot
-----------------------
If you have an TFTP server connected to the switch, it is possible to
directly install the device using the factory image from u-boot
# setup networking and IP of TFP server
rtk network on
setenv ipaddr 10.100.100.99
setenv serverip 10.100.100.20
# get factory image
tftp 0x84000000 factory.bin
# erase firmware partitions
sf probe 0
sf erase 0x100000 0x01f00000
# write firmware to both partitions
sf write ${fileaddr} 0x100000 ${filesize}
sf write ${fileaddr} 0x1080000 ${filesize}
# adjust the boot commands
setenv bootargs "mtdparts=spi0.0:896k(u-boot),64k(u-boot-env),64k(u-boot-env2),15872k(inactive),15872k(firmware2)"
setenv bootcmd "rtk init; bootm 0xb5080000"
# restart
reset
Debug
-----
* Connect serial as per the layout above. Connection parameters: 115200 8N1.
* A tftp server is required, tftpd-hpa works well.
* Power the device, at U-Boot start rapidly hit Esc key to stop autoboot
* Enable network:
rtk network on
* Change ip address of device:
setenv ipaddr 192.168.1.6
* Download initramfs from TFTP server:
tftpboot 0x84000000 192.168.1.111:openwrt-realtek-rtl930x-plasmacloud_psx8-initramfs-kernel.bin
* Boot loaded file:
bootm 0x84000000
Signed-off-by: Harshal Gohel <hg@simonwunderlich.de>
Co-developed-by: Sharadanand Karanjkar <sk@simonwunderlich.de>
Signed-off-by: Sharadanand Karanjkar <sk@simonwunderlich.de>
Link: https://github.com/openwrt/openwrt/pull/19362
Signed-off-by: Hauke Mehrtens <hauke@hauke-m.de>
Plasma Cloud devices use a dual-firmware regions/slots boot mechanism. On
APs, the u-boot is "intelligent" and checks the NOR/NAND partitions (kernel
+ rootfs) for corruption via "datachk". If validation fails, the bootloader
automatically switches to the fallback partition.
On Realtek-based switches, this "datachk" helper is not available.
However, the bootloader still supports two firmware regions/slots.
When flashing a new image, the "inactive" partition is written instead of
overwriting the active one. If no "inactive" partition exists but
"firmware1" is present, the bootloader always treats "firmware1" as
fallback. Only after a successful flash is the `u-boot-env` updated to
select the newly written partition.
On reboot, the bootloader loads the kernel from the new partition and
passes `mtdparts` information as the kernel cmdline. The Plasma Cloud
switch device tree does not override this with a `bootargs` property, so
the active partition layout is honored from cmdline.
Since offsets, sizes, and names of partitions match between the device tree
and cmdline (except the inactive slot), properties and nodes such as
`nvmem-cells` or `compatible` remain fully usable.
This mechanism also allows switching back to the old firmware slot. For
example, if `firmware1` is currently active (`/proc/mtd` shows it), it can
be switched to slot 2 using:
. /lib/upgrade/upgrade_dualboot.sh
set_boot_part 2
reboot
Firmware upgrades use standard `sysupgrade` tarballs, chosen for
compatibility with vendor images. In theory, one can switch between vendor
and OpenWrt with:
sysupgrade -n /tmp/*-squashfs-sysupgrade.bin
Note: configuration files must not be preserved, as they are not compatible
with vanilla OpenWrt.
Signed-off-by: Harshal Gohel <hg@simonwunderlich.de>
Signed-off-by: Sharadanand Karanjkar <sk@simonwunderlich.de>
Link: https://github.com/openwrt/openwrt/pull/19362
Signed-off-by: Hauke Mehrtens <hauke@hauke-m.de>
To be able to read out the ethaddr from the u-boot environment for MAC
address configuration, it is required to also enable the NVMEM layout
parsing code for the U-Boot env layout.
Signed-off-by: Harshal Gohel <hg@simonwunderlich.de>
Signed-off-by: Sharadanand Karanjkar <sk@simonwunderlich.de>
Link: https://github.com/openwrt/openwrt/pull/19362
Signed-off-by: Hauke Mehrtens <hauke@hauke-m.de>
The function of_get_mac_address is not taking care of evaluation the nvmem
address before trying to read out the mac-address properties. The driver
must check whether the return code is -EPROBE_DEFER and stop the probing
process in that case. If the nvmem-cell related driver code finished, the
probe can be redone ad the correct mac-address will appear for the device.
Signed-off-by: Harshal Gohel <hg@simonwunderlich.de>
Signed-off-by: Sharadanand Karanjkar <sk@simonwunderlich.de>
Link: https://github.com/openwrt/openwrt/pull/19362
Signed-off-by: Hauke Mehrtens <hauke@hauke-m.de>
Add calibration variant and ipq-wifi package for Xiaomi AIoT AC2350
Signed-off-by: Igor Dyatlov <dyatlov.igor@gmail.com>
Link: https://github.com/openwrt/openwrt/pull/19707
Signed-off-by: Robert Marko <robimarko@gmail.com>
The ath9k driver creates an ath9k LED by default. Instead of having a
non functional LED, configure it properly and remove the extra as it's
not needed.
It's also a bit funny matching against phy0 and phy1 when both differ
between ath9k and ath10k.
Signed-off-by: Rosen Penev <rosenp@gmail.com>
Link: https://github.com/openwrt/openwrt/pull/19862
Signed-off-by: Robert Marko <robimarko@gmail.com>
LLDP packets must be transmitted on a single port and trapped on a port of
a device which understands LLDP. It must not forward it to other ports to
avoid confusing neighbor information on connected devices.
Signed-off-by: Harshal Gohel <hg@simonwunderlich.de>
Signed-off-by: Sharadanand Karanjkar <sk@simonwunderlich.de>
Link: https://github.com/openwrt/openwrt/pull/19571
Signed-off-by: Hauke Mehrtens <hauke@hauke-m.de>
Driver needs to configure management frame actions
To support LLDP, EAPOL or MSTP, which needs to be trapped to the CPU
instead of being forwarded.
The function to implement the various management frame actions was already
present but not yet registered correctly.
Signed-off-by: Harshal Gohel <hg@simonwunderlich.de>
Signed-off-by: Sharadanand Karanjkar <sk@simonwunderlich.de>
Link: https://github.com/openwrt/openwrt/pull/19571
Signed-off-by: Hauke Mehrtens <hauke@hauke-m.de>
Driver needs to configure management frame actions
To support LLDP, EAPOL or MSTP, which needs to be trapped to the CPU
instead of being forwarded
Signed-off-by: Harshal Gohel <hg@simonwunderlich.de>
Signed-off-by: Sharadanand Karanjkar <sk@simonwunderlich.de>
Link: https://github.com/openwrt/openwrt/pull/19571
Signed-off-by: Hauke Mehrtens <hauke@hauke-m.de>
The functions to enable trapping of management frames are not RTL83xx
specific. It is more appropriate to use the more generic "rtldsa" prefix
for them.
Signed-off-by: Harshal Gohel <hg@simonwunderlich.de>
Signed-off-by: Sharadanand Karanjkar <sk@simonwunderlich.de>
Link: https://github.com/openwrt/openwrt/pull/19571
Signed-off-by: Hauke Mehrtens <hauke@hauke-m.de>
Add new option required to build with VHOST_MENU=y
This option enables two IOCTLs: VHOST_SET_FORK_FROM_OWNER and
VHOST_GET_FORK_FROM_OWNER. These allow userspace applications
to modify the vhost worker mode for vhost devices.
Also expose module parameter 'fork_from_owner_default' to allow users
to configure the default mode for vhost workers.
By default, `VHOST_ENABLE_FORK_OWNER_CONTROL` is set to `y`,
users can change the worker thread mode as needed.
If this config is disabled (n),the related IOCTLs and parameters will
be unavailable.
If unsure, say "Y".
Signed-off-by: John Audia <therealgraysky@proton.me>
Link: https://github.com/openwrt/openwrt/pull/19618
Signed-off-by: Robert Marko <robimarko@gmail.com>
The ath9k driver creates an ath9k LED by default. Instead of having a
non functional LED, configure it properly and remove the extra as it's
not needed.
Signed-off-by: Rosen Penev <rosenp@gmail.com>
Link: https://github.com/openwrt/openwrt/pull/18904
Signed-off-by: Robert Marko <robimarko@gmail.com>
Use macro defined bias types instead of some magic numbers. This can
help reviewers better understand bias types.
Signed-off-by: Shiji Yang <yangshiji66@outlook.com>
Link: https://github.com/openwrt/openwrt/pull/19855
Signed-off-by: Robert Marko <robimarko@gmail.com>
The RTL931x has 14 frontend and at least 26 backend serdes. Currently
the programming functions always need to determine the right backend
serdes from the given frontend serdes on their own.
We plan to provide a consistent serdes mapping to all callers as follows
Frontend SerDes | 0 1 2 3 4 5 6 7 8 9 10 11 12 13
-----------------+------------------------------------------
Backend SerDes 1 | 0 1 2 3 6 7 10 11 14 15 18 19 22 23
Backend SerDes 2 | 0 1 2 4 6 8 10 12 14 16 18 20 22 24
Backend SerDes 3 | 0 1 2 5 6 9 10 13 14 17 18 21 22 25
frontend page "even" frontend SerDes "odd" frontend SerDes
page 0x000-0x03f (analog): page 0x000-0x03f back SDS page 0x000-0x03f back SDS
page 0x100-0x13f (XSGMII1): page 0x000-0x03f back SDS page 0x000-0x03f back SDS+1
page 0x200-0x23f (XSGMII2): page 0x000-0x03f back SDS page 0x000-0x03f back SDS+2
As a first micro step provide some helpers that simply operate on
frontend serdes and will determine the backend serdes on their own.
So rtmdio_931x_read_sds_phy() and rtmdio_931x_write_sds_phy() operate
on backend serdes. While rtmdio_931x_read_sds_phy_**new**() and
rtmdio_931x_write_sds_phy_**new**() operate on frontend serdes.
This is only an intermediate naming convention and will be cleanup
afterwards.
In a first step make use of these new functions whenever we
want to access the analog page. As the pages stay unchanged
in the new functions conversion is as simple as this:
Old:
asds = rtl931x_get_analog_sds(...)
rtmdio_931x_read_sds_phy(asds, ...)
New:
rtmdio_931x_read_sds_phy_new(sds, ...)
Signed-off-by: Markus Stockhausen <markus.stockhausen@gmx.de>
Link: https://github.com/openwrt/openwrt/pull/19818
Signed-off-by: Robert Marko <robimarko@gmail.com>
The ath9k documentation says to use pci168c strings for the compatible
string, probably because the OWL loader uses it to overide bogus pci IDs
like abcd. This is not the case with ath10k and the documentation
explicitly states to use qcom,ath10k.
Signed-off-by: Rosen Penev <rosenp@gmail.com>
Link: https://github.com/openwrt/openwrt/pull/18920
Signed-off-by: Robert Marko <robimarko@gmail.com>
This device does not come with a pci card. It has a slot where one can
get supplied. What's more, nvmem or ieee80211 frequency limits are not
applied here. It can just get removed.
Signed-off-by: Rosen Penev <rosenp@gmail.com>
Link: https://github.com/openwrt/openwrt/pull/18920
Signed-off-by: Robert Marko <robimarko@gmail.com>
The ath9k driver creates an ath9k LED by default. Instead of having a
non functional LED, configure it properly and remove the extra as it's
not needed.
Signed-off-by: Rosen Penev <rosenp@gmail.com>
Link: https://github.com/openwrt/openwrt/pull/18906
Signed-off-by: Robert Marko <robimarko@gmail.com>
The ath9k driver creates an ath9k LED by default. Instead of having a
non functional LED, configure it properly and remove the extra as it's
not needed.
Signed-off-by: Rosen Penev <rosenp@gmail.com>
Link: https://github.com/openwrt/openwrt/pull/18908
Signed-off-by: Robert Marko <robimarko@gmail.com>
The ath9k driver creates an ath9k LED by default. Instead of having a
non functional LED, configure it properly and remove the extra as it's
not needed.
Set the pcie device to qcom,ath10k as the Documentation says, The pci
line implies it's ath9k when it's actually ath10k.
Signed-off-by: Rosen Penev <rosenp@gmail.com>
Link: https://github.com/openwrt/openwrt/pull/18873
Signed-off-by: Robert Marko <robimarko@gmail.com>
Userspace handling is deprecated.
Signed-off-by: Rosen Penev <rosenp@gmail.com>
Link: https://github.com/openwrt/openwrt/pull/18873
Signed-off-by: Robert Marko <robimarko@gmail.com>
The kmod is installed on all filogic mediatek images, even for devices
that do not have any aquantia hardware. Remove it.
Signed-off-by: Paul Donald <newtwen+github@gmail.com>
Link: https://github.com/openwrt/openwrt/pull/19488
[Do not explicitly remove kmod-phy-aquantia from gatonetworks_gdsp]
Signed-off-by: Hauke Mehrtens <hauke@hauke-m.de>
Move append-teltonika-metadata to image-commands.mk and unify over different targets.
This method can be used to create valid "factory" images for most of Teltonika devices.
Signed-off-by: Simonas Tamošaitis <simsasss@gmail.com>
Link: https://github.com/openwrt/openwrt/pull/19401
Signed-off-by: Hauke Mehrtens <hauke@hauke-m.de>
The ath9k driver creates an ath9k LED by default. Instead of having a
non functional LED, configure it properly and remove the extra as it's
not needed.
Signed-off-by: Rosen Penev <rosenp@gmail.com>
Tested-by: Zoltan HERPAI wigyori@uid0.hu
Link: https://github.com/openwrt/openwrt/pull/18907
Signed-off-by: Hauke Mehrtens <hauke@hauke-m.de>
Support in mt76 has existed for quite a while. Use it.
Signed-off-by: Rosen Penev <rosenp@gmail.com>
Link: https://github.com/openwrt/openwrt/pull/19799
Signed-off-by: Hauke Mehrtens <hauke@hauke-m.de>
This commit adds support for the WAVLINK WL-WN586X3 Rev B, which swaps
the 16MB NOR flash for an 128MB NAND flash chip, and uses UBI for
data partition. This commit utilizes the previous submitted dtsi that
includes common hardware for a few Wavlink routers.
Hardware
--------
- SOC: MediaTek MT7981B
- RAM: 256MB DDR3
- Flash: 128MB SPI-NAND (ESMT F50L1G41LB)
- Ethernet: 2x1Gb Lan 1x1Gb Wan
- WiFi: MediaTek MT7981B 2x2 DBDC 802.11ax 2T2R (2.4/5) with 4 external and 1 internal antennae
- LEDs: 2xLan 1x Wan 1x WIFI 1xSTATUS
Installation
------------
Flashing over the vendor WebUI has been tested and unsuccessful (YMMV).
The image need to be flashed via TFTP which can be activated over the onboard UART serial console:
1. Connect UART: TX->board RX, RX->board TX, GND->board GND.
2. Connect PC to router lan port.
3. Setup the tftp server on PC, set IP to 192.168.10.100.
4. Power on the device. Interrupt boot countdown at uboot boot menu and select 2. Upgrade firmware option.
5. Input the image name and start flashing.
Sample uboot menu:
```
*** U-Boot Boot Menu ***
1. Startup system (Default)
2. Upgrade firmware
3. Upgrade ATF BL2
4. Upgrade ATF FIP
5. Upgrade single image
6. Load image
0. U-Boot console
```
NOTE: Do not use the intermediate image here which is for Rev A only:
https://github.com/themaverickdm/firmware-misc/tree/main/wavlink/wl-wn586x3
MAC Addresses
-------------
LAN: 80:3F:5D:xx:xx:x1 (hw, 0x44e, ASCII encoded)
WAN: 80:3F:5D:xx:xx:x2 (hw, 0x460, ASCII encoded)
2G: 80:3F:5D:xx:xx:x3 (factory, 0x4, raw binary, also on label)
5G: 80:3F:5D:xx:xx:x3 (Same as 2G)
Signed-off-by: Zhenfu Shi <i0ntempest@i0ntempest.com>
Link: https://github.com/openwrt/openwrt/pull/19785
Signed-off-by: Hauke Mehrtens <hauke@hauke-m.de>
CREALITY BOX WB01 is small footprint router based on MediaTek MT7688,
is a device intended to interface Creality brand 3D printers to a cloud service.
Specifications:
- SoC: MediaTek MT7688AN @ 580MHz
- RAM: DDR2 128M (Winbond W971GG6SB-25)
- Flash: BoyaMicro BY25Q128AS (16 MiB, SPI NOR) handled by BoHong bh25q128as driver
- WiFi: 2.4GHz 1T1R internal panel antenna
- Ethernet: 1x LAN (10/100)
- USB: 2x USB2.0 port (Genesys Logic GL850G 2 port USB 2.0 hub)
- UART: 3.3V, TX, RX, GND / 56700 8N1 / only pads on PCB
- microSD SD-XC Class 10 slot
- micro USB input (for power only)
- reset button
- FCC ID: 2AXH6CREALITY-BOX
MAC addresses as verified by OEM firmware:
vendor OpenWrt source
LAN eth0 factory 0x2e
2.4GHz phy0-ap0 factory 0x04 (label)
LEDs
color vendor OpenWRT configurable
red SD card activity - yes
green Cloud connectivity status yes
blue LAN activity eth0 yes
yellow WIFI activity phy0tpt yes
Return to OEM & debrick
- download "cxsw_update.tar.bz2" from manufacturer site
- extract archive to FAT32 USB stick root
- put USB stick in USB2 port
- press & hold reset button
- power on device while holding reset
- wait approx 10 sec
- release reset button
Installation with SD Card
- power on device
- wait for device to finish starting
- copy "openwrt-ramips-mt76x8-creality_wb-01-squashfs-cxsw_update.tar.bz2"
to root of FAT32 SD card
- rename openwrt-ramips-mt76x8-creality_wb-01-squashfs-cxsw_update.tar.bz2
to "cxsw_update.tar.bz2"
- put SD card in device
- device will install OpenWRT on internal flash
Installation via telnet:
- extract the "factory.bin" and "install.sh" from newly created
openwrt-ramips-mt76x8-creality_wb-01-squashfs-cxsw_update.tar.bz2
to FAT32 USB stick root
- telnet to 10.10.10.254, user: root, password: cxswprin
- plug the USB in USB1 port
- cd /media/usbdisk/
- sh install.sh
- device will write "factory.bin" to internal flash
Co-authored-by: George Brooke <figgyc@figgyc.uk>
Co-authored-by: Peca Nesovanovic <peca.nesovanovic@sattrakt.com>
Co-authored-by: shivajiva101 <github.com/shivajiva101>
Co-authored-by: Axel Sepulveda <ansepulveda@uc.cl>
Signed-off-by: Axel Sepulveda <ansepulveda@uc.cl>
Link: https://github.com/openwrt/openwrt/pull/19686
Signed-off-by: Hauke Mehrtens <hauke@hauke-m.de>
mt7531 switch reset delay time is hard coded in the driver. The
"reset-assert-us" and "reset-deassert-us" won't take effect.
Signed-off-by: Shiji Yang <yangshiji66@outlook.com>
Link: https://github.com/openwrt/openwrt/pull/19741
Signed-off-by: Hauke Mehrtens <hauke@hauke-m.de>
Use tabs to align and remove some unnecessary spaces.
Signed-off-by: Shiji Yang <yangshiji66@outlook.com>
Link: https://github.com/openwrt/openwrt/pull/19741
Signed-off-by: Hauke Mehrtens <hauke@hauke-m.de>
They were lost when ported to the 6.12 kernel.
Signed-off-by: Shiji Yang <yangshiji66@outlook.com>
Link: https://github.com/openwrt/openwrt/pull/19741
Signed-off-by: Hauke Mehrtens <hauke@hauke-m.de>
The Mediatek pinctrl driver can only accepts drive-strength values
enumerated in "dt-bindings/pinctrl/mt65xx.h".
Signed-off-by: Shiji Yang <yangshiji66@outlook.com>
Link: https://github.com/openwrt/openwrt/pull/19741
Signed-off-by: Hauke Mehrtens <hauke@hauke-m.de>
Add the missing "device_type" property to fix the memory node. The
Linux kernel can not get the memory size without it. Though u-boot
can automatically fixup the memory node by adding the "device_type"
and "reg" properties if the CONFIG_ARCH_FIXUP_FDT_MEMORY symbol is
enabled, it's better not to rely on this optional feature. This
patch also adds the reg address for the memory node name to follow
the naming rules.
Signed-off-by: Shiji Yang <yangshiji66@outlook.com>
Link: https://github.com/openwrt/openwrt/pull/19741
Signed-off-by: Hauke Mehrtens <hauke@hauke-m.de>
When testing LLDP and STP, we observed that locally generated multicast
packets (e.g. LLDP, STP) were not restricted to the designated output
port(s). For example, when transmitting on `lan1`, the same packet was also
forwarded to other ports such as `lan2`.
Steps to reproduce:
1. Configure lldpd to use `lan1` in UCI and restart the service
2. Connect devices to `lan1` and `lan2`
3. Observe that the device on `lan2` still receives LLDP packets
The issue was caused by an incorrect `FWD_TYPE` setting in the TX CPU TAG,
which failed to enforce the selected egress port(s).
Fix this by updating the TX CPU TAG to set `FWD_TYPE` correctly, ensuring
that locally generated packets are transmitted only on the intended
port(s).
Signed-off-by: Issam Hamdi <ih@simonwunderlich.de>
Link: https://github.com/openwrt/openwrt/pull/19802
Signed-off-by: Hauke Mehrtens <hauke@hauke-m.de>
Product name: Acer Predator Connect W6x
Product link: https://www.acer.com/us-en/predator/networking/wi-fi/predator-connect-w6x/pdp/FF.G2TTA.001
* Specifications:
SOC: MT7986AV
RAM: 1024MB
Flash: 256 MB SPI NAND
Ports: 4 LAN (1G) & 1 WAN (2.5G)
WIFI: MT7976GN + MT7976AN
LED: 1, ws2812b controller
* Installation via UART:
1. Configure TFTP server with IP 192.168.1.66. Copy `openwrt-mediatek-filogic-acer_predator-w6x-initramfs-kernel.bin` to TFTP root and rename to `predator.bin`
2. Interrupt boot by pressing 0 on startup or select `U-Boot Console` in U-Boot Boot Menu.
3. Run setenv `serverip 192.168.1.66; setenv ipaddr 192.168.1.1; tftpboot 0x46000000 predator.bin; fdt addr $(fdtcontroladdr); fdt rm /signature; bootm` in uboot console.
4. Wait for boot complete on Openwrt initramfs env.
** You can back up the MTD partitions at this point. Refer to Backup Instructions section.
5. On client PC, transfer `openwrt-mediatek-filogic-acer_predator-w6x-squashfs-sysupgrade.bin` to /tmp/ - `scp -O openwrt-mediatek-filogic-acer_predator-w6x-squashfs-sysupgrade.bin root@192.168.1.1:/tmp/sysupgrade.bin`
6. On router, run sysupgrade - `sysupgrade -n /tmp/sysupgrade.bin`
Should now boot to Openwrt. Ensure it boots automatically to Openwrt by replugging the power.
* Backup Instructions:
Layout from stock firmware:
```
[ 0.968731] Creating 10 MTD partitions on "nmbm_spim_nand":
[ 0.974297] 0x000000000000-0x000000100000 : "BL2"
[ 0.979424] 0x000000100000-0x000000180000 : "u-boot-env"
[ 0.985032] 0x000000180000-0x000000380000 : "Factory"
[ 0.990379] 0x000000380000-0x000000580000 : "FIP"
[ 0.995378] 0x000000580000-0x000000600000 : "prod"
[ 1.000461] 0x000000600000-0x000000700000 : "dual"
[ 1.005527] 0x000000700000-0x000000800000 : "pot"
[ 1.010516] 0x000000800000-0x000006c00000 : "ubi"
[ 1.015626] 0x000006c00000-0x00000d000000 : "ubi1"
[ 1.020801] 0x00000d000000-0x00000d800000 : "storage"
```
Mapping in initramfs env:
```
dev: size erasesize name
mtd0: 00100000 00020000 "bl2"
mtd1: 00080000 00020000 "u-boot-env"
mtd2: 00200000 00020000 "factory"
mtd3: 00200000 00020000 "fip"
mtd4: 00020000 00020000 "prod"
mtd5: 00100000 00020000 "dual"
mtd6: 00100000 00020000 "pot"
mtd7: 06400000 00020000 "ubi"
mtd8: 06400000 00020000 "ubi1"
mtd9: 00800000 00020000 "storage"
```
1. While in openwrt initramfs environment, back up all the partitions by running the following:
```
cat /dev/mtd0 > /tmp/bl2.bin
cat /dev/mtd1 > /tmp/u-boot-env.bin
cat /dev/mtd2 > /tmp/factgory.bin
cat /dev/mtd3 > /tmp/fip.bin
cat /dev/mtd4 > /tmp/prod.bin
cat /dev/mtd5 > /tmp/dual.bin
cat /dev/mtd6 > /tmp/pot.bin
cat /dev/mtd7 > /tmp/ubi.bin
cat /dev/mtd8 > /tmp/ubi1.bin
cat /dev/mtd9 > /tmp/storage.bin
```
2. Transfer files to client PC for safekeeping. On client PC, run `scp -O root@192.168.1.1:/tmp/*.bin ./`
* Restore to Stock Firmware:
1. Boot to openwrt initramfs env.
2. Confirm layout matches as follows by running `cat /proc/mtd`. Ensure dev `mtd7` is named `ubi`:
```
dev: size erasesize name
mtd0: 00100000 00020000 "bl2"
mtd1: 00080000 00020000 "u-boot-env"
mtd2: 00200000 00020000 "factory"
mtd3: 00200000 00020000 "fip"
mtd4: 00020000 00020000 "prod"
mtd5: 00100000 00020000 "dual"
mtd6: 00100000 00020000 "pot"
mtd7: 06400000 00020000 "ubi"
mtd8: 06400000 00020000 "ubi1"
mtd9: 00800000 00020000 "storage"
```
3. Detach `ubi` partition - `ubidetach -p /dev/mtd7`
4. Transfer stock firmware's `ubi.bin` to router from client PC: `scp -O ubi.bin root@192.168.1.1/tmp/`
5. Format and replace with backup `ubiformat /dev/mtd7 -y -f /tmp/ubi.bin`
6. Reboot and you should now be back on stock firmware.
* LEDS:
LED color can be controlled by specifying values in GRB format in `/sys/class/leds/rgb:status/multi_intensity`. Default is `255 255 255` (white).
Example: `echo '75 0 130' > /sys/class/leds/rgb:status/multi_intensity`
LED brightness can be changed by specifying the value from 0-255 in /sys/class/leds/rgb:status/brightness. Default is `255` (full brightness).
Example: `echo 100 > /sys/class/leds/rgb:status/brightness`
For persistence across reboots, put the relevant command(s) in /etc/rc.local.
* Notes:
root access on stock firmware:
Before flashing openwrt, and while in openwrt initramfs env:
1. Mount /dev/ubi0_2: `mkdir /tmp/ubi0_2; mount -t ubifs /dev/ubi0_2 /tmp/ubi0_2`
2. Modify `/tmp/ubi0_2/upper/etc/passwd` and change line with `root❌0:0...` to `root::0:0...`, remove the `x`.
3. Save and reboot.
4. You should now be able to log in with root and empty password while booted in stock firmware.
While on Openwrt, subsequent upgrades can be made by sysupgrade, or via Luci. UART should not be necessary unless you want to revert to stock firmeware.
Signed-off-by: Qing W <ses1er@gmail.com>
Link: https://github.com/openwrt/openwrt/pull/19754
Signed-off-by: Hauke Mehrtens <hauke@hauke-m.de>
XikeStor (Seeker) SKS8310-8X is a 8 ports Multi-Gig switch, based on
RTL9303.
Specifications:
- SoC : Realtek RTL9303
- RAM : DDR3 512 MiB
- Flash : SPI-NOR 32 MiB (Macronix)
- Ethernet : 8x 1/2.5/10 Gbps (SFP+)
- LEDs/Keys (GPIO) : 1x/1x
- UART : "Console" port on the front panel
- type : RS-232C
- connector : RJ-45
- settings : 115200 8N1
- Power : 12 VDC, 2 A
Flash instruction using initramfs image:
1. Prepare TFTP server & connect to serial port.
2. Connect your computer to one of the ports on SKS8310-8X with a
suitable SFP module (some work, some don't).
3. Power on SKS8310-8X and interrupt autoboot with Shift + A.
4. Use Shift + Q to drop from vendor CLI to U-Boot CLI.
5. Enable networking within U-Boot.
> rtk network on
6. Set switch IP and TFTP server IP (optional, adjust to your setup).
> setenv ipaddr <ip>
> setenv serverip <ip>
7. Download initramfs image from TFTP server.
> tftpboot 0x82000000 <image name>
8. Boot with the downloaded image.
> bootm 0x82000000
9. With rambooted OpenWrt, backup the stock firmware if needed.
10. Copy sysupgrade image to the device.
11. Perform sysupgrade with the sysupgrade image.
12. After reboot, you should have functional OpenWrt.
Reverting to stock firmware:
1. Download latest firmware from XikeStor and upload to your device.
1. Write firmware with 'sysupgrade -F'.
2. After reboot, stock firmware should boot automatically.
Co-authored-by: Jonas Jelonek <jelonek.jonas@gmail.com>
Signed-off-by: Alexandra Alth <alexandra@alth.de>
Signed-off-by: Jonas Jelonek <jelonek.jonas@gmail.com>
Link: https://github.com/openwrt/openwrt/pull/19782
Signed-off-by: Hauke Mehrtens <hauke@hauke-m.de>
This makes 5ghz WiFi work out of the box on these devices, eliminating
the need to flash a magic blob to the radio partition.
This was found by user BulldozerBSG on the OpenWRT Forums:
https://forum.openwrt.org/t/tp-link-archer-mr600-exploration/65489/20
All credit belongs to them. I can confirm the correctness of the
findings. At least one other user (Iggy87100) confirmed them too.
Signed-off-by: Stefan Dösinger <stefandoesinger@gmail.com>
Link: https://github.com/openwrt/openwrt/pull/19790
Signed-off-by: Hauke Mehrtens <hauke@hauke-m.de>
The 6.12 kernel has exceeded the kernel size limit. the buildbot
can no longer build images for them. Developers can try switching
the kernel type to zImage to enable them again.
Signed-off-by: Shiji Yang <yangshiji66@outlook.com>
Link: https://github.com/openwrt/openwrt/pull/19826
Signed-off-by: Robert Marko <robimarko@gmail.com>
This is an automatically generated commit which aids following Kernel patch
history, as git will see the move and copy as a rename thus defeating the
purpose.
For the original discussion see:
https://lists.openwrt.org/pipermail/openwrt-devel/2023-October/041673.html
Signed-off-by: Andre Heider <a.heider@gmail.com>
Whilst testing Hasivo s1100wp-8gt-se LED configuration, several error
messages were presented which didn't indicate which led_set they were
referencing, nor what the value was that caused the invalid configuration.
Migrate to use dev_ print messages for this function.
And tidy up both when the error message is reported (don't show it when
an led_set isn't in the DTS) and what details the message presents.
Signed-off-by: Bevan Weiss <bevan.weiss@gmail.com>
Link: https://github.com/openwrt/openwrt/pull/19791
Signed-off-by: Robert Marko <robimarko@gmail.com>
Add defines for RTL930x and RTL931x led_set 'modes' (to avoid magic numbers
in dts files).
Signed-off-by: Bevan Weiss <bevan.weiss@gmail.com>
Link: https://github.com/openwrt/openwrt/pull/19791
Signed-off-by: Robert Marko <robimarko@gmail.com>
Remove old kernel support to prepare for the next LTS release.
Signed-off-by: Shiji Yang <yangshiji66@outlook.com>
Link: https://github.com/openwrt/openwrt/pull/19821
Signed-off-by: Nick Hainke <vincent@systemli.org>
We have not received any negative feedback in the past three months.
It's time to switch the default kernel to 6.12.
Signed-off-by: Shiji Yang <yangshiji66@outlook.com>
Link: https://github.com/openwrt/openwrt/pull/19821
Signed-off-by: Nick Hainke <vincent@systemli.org>
All of this uses OF now. No need to keep platform data around.
Signed-off-by: Rosen Penev <rosenp@gmail.com>
Link: https://github.com/openwrt/openwrt/pull/19804
Signed-off-by: Robert Marko <robimarko@gmail.com>
This commit repeats the mdio function relocation from the other targets.
In short that means:
- phy read/write functions are moved away from the phy driver
- SerDes read/write functions are moved away from the dsa driver
- All gets consolidated into the mdio driver (inside the ethernet driver)
This is mostly a copy/paste to keep the changes small. The SerDes phy mapping
and the simplification of the central bus functions will come later.
Signed-off-by: Markus Stockhausen <markus.stockhausen@gmx.de>
Link: https://github.com/openwrt/openwrt/pull/19743
Signed-off-by: Robert Marko <robimarko@gmail.com>
The IPQ4019 datasheet indicates that the maximum supported SPI
frequency is 25 MHz. My experiment on SKSpruce WIA3300-20 shows
that exceeding this threshold can lead to instability of SPI
peripheral. Limit the SPI clock frequency to the QSDK recommended
value 24MHz to enhance stability.
Signed-off-by: Shiji Yang <yangshiji66@outlook.com>
Link: https://github.com/openwrt/openwrt/pull/19744
Signed-off-by: Robert Marko <robimarko@gmail.com>
The support is done. Let's set 6.12 as testing kernel.
Signed-off-by: Pawel Dembicki <paweldembicki@gmail.com>
Link: https://github.com/openwrt/openwrt/pull/19152
Signed-off-by: Hauke Mehrtens <hauke@hauke-m.de>
Support in mt76 has existed for quite a while. Use it.
Signed-off-by: Rosen Penev <rosenp@gmail.com>
Link: https://github.com/openwrt/openwrt/pull/19771
Signed-off-by: Hauke Mehrtens <hauke@hauke-m.de>
Now that the driver has been enhanced for RTL931x devices and
the DTS is up to date, activate the needed kernel configuration
for the two RTL931x subtargets.
Signed-off-by: Markus Stockhausen <markus.stockhausen@gmx.de>
Link: https://github.com/openwrt/openwrt/pull/19776
Signed-off-by: Hauke Mehrtens <hauke@hauke-m.de>
The RTL8231 auxiliary controller is not defined in the rtl931x.dtsi.
Additionally the pinmux is configured at the wrong address. Fix
this.
Signed-off-by: Markus Stockhausen <markus.stockhausen@gmx.de>
Link: https://github.com/openwrt/openwrt/pull/19776
Signed-off-by: Hauke Mehrtens <hauke@hauke-m.de>
The auxiliary RTL8231 controller driver is missing RTL931x support.
Add it by defining the proper register and matching compatible.
Signed-off-by: Markus Stockhausen <markus.stockhausen@gmx.de>
Link: https://github.com/openwrt/openwrt/pull/19776
Signed-off-by: Hauke Mehrtens <hauke@hauke-m.de>
The Realtek DTS's use several macros for convenient phy/port definition.
These are repeated for the RTL83xx targets and most are missing for the
RTL93xx targets. In the near future we want to add high port count
switches with 1GBit Ethernet for them too. As a preparation provide a
central include so the definition is only needed once and is available
for all targets.
Signed-off-by: Markus Stockhausen <markus.stockhausen@gmx.de>
Link: https://github.com/openwrt/openwrt/pull/19772
Signed-off-by: Hauke Mehrtens <hauke@hauke-m.de>
Since 6.12 is now default, drop 6.6 support.
Signed-off-by: Goetz Goerisch <ggoerisch@gmail.com>
Link: https://github.com/openwrt/openwrt/pull/19778
Signed-off-by: Nick Hainke <vincent@systemli.org>
Let's switch the ipq40xx target to use kernel 6.12 by default.
Signed-off-by: Goetz Goerisch <ggoerisch@gmail.com>
Link: https://github.com/openwrt/openwrt/pull/19778
Signed-off-by: Nick Hainke <vincent@systemli.org>
We are using upstream otto timer. Delete some downstream leftovers.
Signed-off-by: Markus Stockhausen <markus.stockhausen@gmx.de>
Link: https://github.com/openwrt/openwrt/pull/19769
Signed-off-by: Robert Marko <robimarko@gmail.com>
Drop our downstream driver in favor of an upstream existing driver which
is available starting from v6.13.
Signed-off-by: Jonas Jelonek <jelonek.jonas@gmail.com>
Link: https://github.com/openwrt/openwrt/pull/19736
Signed-off-by: Robert Marko <robimarko@gmail.com>
Adapt the device tree definitions of rtl93xx devices and the base dtsi
for rtl930x and rtl931x to match with what's expected by the recently
backported RTL9300 I2C driver.
Signed-off-by: Jonas Jelonek <jelonek.jonas@gmail.com>
Link: https://github.com/openwrt/openwrt/pull/19736
Signed-off-by: Robert Marko <robimarko@gmail.com>
Backport/add all patches for the upstream RTL9300 I2C driver.
The upstream driver was added in 6.13 and was heavily based on our
downstream driver except for how the multiplexing behaviour is handled.
This driver was working fine with basic SFP operation on RTL930x devices
but there was no support for RTL931x though.
Major advantage over our downstream driver is: The multiplexing
behaviour is handled completely by the driver. Thus, there's no need for
a separate rtl9300-mux driver as we had it downstream. Moreover, this
simplifies the DTS of affected devices a lot since we can now move the
controller definition - which is in the DTS of each device so far - to
the base DTSI.
Currently pending patches are also included because the progress on
getting this upstream seems really slow right now, albeit upstream
maintainers may require several changes to the current state.
These include:
- patches fixing several issues in the driver
- patches doing a refactoring of the driver and adding support for RTL931x
See the commit messages included in each patch to have details on the
changes.
Signed-off-by: Jonas Jelonek <jelonek.jonas@gmail.com>
Link: https://github.com/openwrt/openwrt/pull/19736
Signed-off-by: Robert Marko <robimarko@gmail.com>
In the conversion to dts, qca,led-pin was used for both interfaces.
Unfortunately, it's mutually exclusive with gpio-controller which made
it not do anything.
Fixes: 949e1a0 ("mpc85xx: tl-wdr4900: move platform code to dts")
Signed-off-by: Rosen Penev <rosenp@gmail.com>
Link: https://github.com/openwrt/openwrt/pull/19758
Signed-off-by: Robert Marko <robimarko@gmail.com>
Modernize the target slightly to use kernel+dtb FIT images in all
subtargets. LZMA compression will be used for the cortexa53 devices,
and we'll stay conservative and use gzip for the cortexa7/a8 devices
due to performance differences.
Tested-on:
- Linksprite pcDuino v2 (cortexa8 / A10)
- Olinuxino Micro (cortexa7 / A20)
- Banana Pi M2 Berry (cortexa7 / V40)
- Banana Pi P2 Zero (cortexa7 / H2+)
- Xunlong Orange Pi 2 (cortexa7/ H3)
- OrangePi PC Zero 2 (cortexa53 / H616)
Signed-off-by: Zoltan HERPAI <wigyori@uid0.hu>
This fixes intermittent dmesg errors
"nss_port5_rx_clk_src: rcg didn't update its configuration."
Signed-off-by: Marko Mäkelä <marko.makela@iki.fi>
Link: https://github.com/openwrt/openwrt/pull/19620
Signed-off-by: Robert Marko <robimarko@gmail.com>
While checking setup routines for stability and completeness,
random RTL838x SoC I/O areas were intentionally overwritten.
As soon as L2_CTRL_1->FAST_AGE_OUT is set to 1, the system
stalls during bootup. Analysis shows that it loops endlessly
in rtl838x_hw_stop()
/* Flush L2 address cache */
if (priv->family_id == RTL8380_FAMILY_ID) {
for (int i = 0; i <= priv->cpu_port; i++) {
sw_w32(1 << 26 | 1 << 23 | i << 5, priv->r->l2_tbl_flush_ctrl);
do { } while (sw_r32(priv->r->l2_tbl_flush_ctrl) & (1 << 26));
}
This is exactly the same logic as in the vendor GPL. There
are no hints about possible timeouts or issues. The reason is
still unclear. Nevertheless harden the function for further fuzzy
tests. Do this by resetting the configuration value to its SoC
default.
Additionally convert some shifts to BIT() for better readability.
Signed-off-by: Markus Stockhausen <markus.stockhausen@gmx.de>
Link: https://github.com/openwrt/openwrt/pull/19679
Signed-off-by: Robert Marko <robimarko@gmail.com>
`loglevel=8` causes the kernel to output all logs, including debug logs, at boot time
It is enabled by default on the upstream eval board because it is aimed at developer debugging.
Most devices reference the eval board directly without modification, and the debug log should be hidden at release
Signed-off-by: Coia Prant <coiaprant@gmail.com>
Link: https://github.com/openwrt/openwrt/pull/19714
Signed-off-by: Robert Marko <robimarko@gmail.com>
The bootloader on these devices uses 0x81000000 as load address for the
compressed image. Since the kernel uses a load address 0x80100000, this
only leaves a space of 15 MiB for the uncompressed image. For larger
images, the compressed data starts to get overwritten, and at some point
the boot will fail:
## Booting image from partition ... 0
## Booting kernel from Legacy Image at 81000000 ...
Version: 9.9.9.9
Created: 2025-08-07 14:56:09 UTC
Data Size: 6756645 Bytes = 6.4 MB
Checksum ... OK
Uncompressing ... LZMA: uncompress or overwrite error 1 - must RESET board to recover
Currently, initramfs images with default config are already over the
limit. And while they still happen to work regardless, adding additional
packages easily pushes the size so much that the boot fails.
Fix this by switching to rt-loader (which relocates the data to the
upper end of the RAM before decompression). The switch includes regular
kernel images to avoid this becoming an issue again in the future.
Signed-off-by: Jan Hoffmann <jan@3e8.eu>
Link: https://github.com/openwrt/openwrt/pull/19734
Signed-off-by: Robert Marko <robimarko@gmail.com>
Once tested this will go upstream.
Signed-off-by: Markus Stockhausen <markus.stockhausen@gmx.de>
Link: https://github.com/openwrt/openwrt/pull/19468
Signed-off-by: Robert Marko <robimarko@gmail.com>
Previous implementation was directly copied from rtl930x and was not
working. Table field offsets are different between rlt931x and rtl930x
Signed-off-by: Harshal Gohel <hg@simonwunderlich.de>
Signed-off-by: Sharadanand Karanjkar <sk@simonwunderlich.de>
Link: https://github.com/openwrt/openwrt/pull/19580
Signed-off-by: Robert Marko <robimarko@gmail.com>
Add usb_vbus ref to usb device.
Signed-off-by: Andrey Safonov <andrey.safonov@gmail.com>
Link: https://github.com/openwrt/openwrt/pull/19698
Signed-off-by: Robert Marko <robimarko@gmail.com>
Add fixed regulator for M.2 slot for Bananapi BPI-RV2
Signed-off-by: Andrey Safonov <andrey.safonov@gmail.com>
Link: https://github.com/openwrt/openwrt/pull/19697
Signed-off-by: Robert Marko <robimarko@gmail.com>
The .rma_bpdu_fld_pmask is not used anywhere in the code for RTL930x nor
RTL931x. But the RTL930x was still initializing this member. To avoid
problems in the future, simply initialize it also on RTL931x.
Signed-off-by: Harshal Gohel <hg@simonwunderlich.de>
Signed-off-by: Sharadanand Karanjkar <sk@simonwunderlich.de>
Link: https://github.com/openwrt/openwrt/pull/19569
Signed-off-by: Hauke Mehrtens <hauke@hauke-m.de>
Neither the RTL930x not the RT931x use the BPDU flooding mechanism which
was used for other SoCs. At the same time, the RTL931x must use the same
debugfs initialization function as RTL930x.
Signed-off-by: Harshal Gohel <hg@simonwunderlich.de>
Signed-off-by: Sharadanand Karanjkar <sk@simonwunderlich.de>
Link: https://github.com/openwrt/openwrt/pull/19569
Signed-off-by: Hauke Mehrtens <hauke@hauke-m.de>
This commit renames the network ports of the Minisforum MS-A2
Mini PC: the two 2.5G RJ45 ports are now named lan1 and lan2,
and the two 10G SFP+ ports sfp1 and sfp2.
All four ports are also added to the default lan interface.
--- Hardware Highlights ---
AMD Ryzen™ 9 9955HX/7945HX
Dual DDR5-5600MHz, up to 96GB
2x 10G SFP+, 2x 2.5G RJ45
WiFi 6E, Bluetooth 5.3
Built-in PCIe x16 Slot
Signed-off-by: Til Kaiser <mail@tk154.de>
Link: https://github.com/openwrt/openwrt/pull/19689
Signed-off-by: Hauke Mehrtens <hauke@hauke-m.de>
The RTL930x mdio functions are scattered around the code. Relocate
them to the bus (still inside the ethernet driver). With this change
the phy identification looks into the proper registers. The SerDes
phy identifier (register 2/3) must be changed.
Additionally provide a consistent SerDes register access through the
mdio bus. Until now when a SerDes directly drives a SFP module there
is no clear rule of how to handle its register set that consists of
two parts:
- c22 phy registers 0-15 live in the fiber page (2) of the SerDes
- other SerDes specific registers exist in pages before and after
The mdio bus and other SerDes functions are a wild mix of directly
looking into page 2 or just using self defined methods to access
data.
Adapt the bus to the new consistent phy interface that mixes the
SerDes register set like classic Realtek phys do it.
- Use register 31 as page select (already in the bus)
- Always keep the common registers 0-15 in place and read fiber page
- Map the SerDes internal registers into the upper vendor specific
registers 16-23 according to the page select register (31).
That gives a register mapping as follows:
+-----------------------+-----------------------+---------------+-------------+
| reg 0x00-0x0f | reg 0x10-0x17 | reg 0x18-0x1e | reg 0x1f |
+-----------------------+-----------------------+---------------+-------------+
| SerDes fiber page (3) | real SerDes registers | zero | SerDes page |
| registers 0 - 15 | in packages of 8 | | select reg |
+-----------------------+-----------------------+---------------+-------------+
Example to make it as clear as possible.
SerDes registers on a RTL930x show
Page / Reg | 0x00 0x01 0x02 0x03 0x04 0x05 0x06 0x07 0x08 0x09 0x0A 0x0B ...
-------------+----------------------------------------------------------------
0 - SDS | 0C03 0F00 7060 7106 074D 0EBF 0F0F 0359 5248 0000 0F80 0000 ...
1 - SDS_EXT | 0000 0000 85FA 8C6D 5CCC 0000 20D8 0003 79AA 8C64 00C3 1482 ...
2 - FIB | 1140 6189 001C CA40 01A0 0000 0000 0004 0000 0000 0000 0000 ...
3 - FIB_EXT | 1140 6109 001C CA40 01A0 0000 0000 0004 0000 0000 0000 0000 ...
This translates to this phy layout
| SerDes fiber registers normal SerDes registers zero p.sel
Page / Reg | 0x00 0x01 0x02 0x03 ... 0x10 0x11 0x12 0x13 ... 0x18 ... 0x1f
-------------+---------------------------------------------------------------
0 | 1140 6189 001C CA40 ... 0C03 0F00 7060 7106 ... 0000 ... 0000
1 | 1140 6189 001C CA40 ... 5248 0000 0F80 0000 ... 0000 ... 0001
...
4 | 1140 6189 001C CA40 ... 0000 0000 85FA 8C6D ... 0000 ... 0004
Signed-off-by: Markus Stockhausen <markus.stockhausen@gmx.de>
Link: https://github.com/openwrt/openwrt/pull/19692
Signed-off-by: Robert Marko <robimarko@gmail.com>
Some known RTL93xx devices like the Linksys LGS328C or LGS352C are
NAND based. These require additional drivers and packages (e.g. UBI).
The current subtargets are already taylored down for devices with
only 16MB flash. Adding features that are not used will only make
the storage situation more complicated.
Add two new subtargets for RTL93xx that include the basic NAND, UBI
and MTD features. To achieve this do the following:
- Create new subtarget folders
- Copy the existing config and makefiles over
- Add the basic additional features
- Mark them as SOURCE-ONLY
- Add empty image makefiles
- Remove unneded NAND/MTD features from existing configs
Signed-off-by: Markus Stockhausen <markus.stockhausen@gmx.de>
Link: https://github.com/openwrt/openwrt/pull/19700
Signed-off-by: Robert Marko <robimarko@gmail.com>
These devices need a tiny (<8MB) initramfs. There are first
occurrences where this fails with newer kernels and diagnostic
packages.
Switch the recipe over to use lzma compression and rt-loader.
Signed-off-by: Markus Stockhausen <markus.stockhausen@gmx.de>
Link: https://github.com/openwrt/openwrt/pull/19687
Signed-off-by: Hauke Mehrtens <hauke@hauke-m.de>
This is an industrial 4G router equipped with OpenWrt SNAPSHOT OEM
customized version
WARNING: The original firmware device tree is modified from evb
boards, and the device tree name is evb board. This submitted device
tree is a modified version, which deletes the non-this-device parts
and adds GPIO watchdog.
Specification:
- SoC: MediaTek MT7628NN
- Flash: 16 MB
- RAM: 128 MB
- Power: DC 5V-36V 1.5A
- Ethernet: 1x WAN [slot not install], 1x LAN (10/100 Mbps)
- Wireless radio: 802.11n 2.4g-only [antenna not install]
- LED:
System/Power (RUN): GPIO/37 active-low
Modem: GPIO/3 active-low
RF (Modem Signal): GPIO/2 active-low
- Button:
WPS / RESET: GPIO/11 active-low
- UART: 1x UART on PCB - 115200 8N1
- Serial / COM: 1X RS232/RS485 on board (GPIO/6 hi:RS485 lo:RS232)
- GPIO Watchdog: GPIO/0 mode=toggle timeout=1s
- Modem: 1x Built-in modem on board (Power: GPIO/4 active-high)
- PCIe: 1x miniPCIe for modem [slot not install]
- SIM Slots: 1x SIM Slots
Issue:
- Factory partition not store mac address on original firmware
Flash instruction:
Using SSH/Telnet:
1. Connect the board to the computer via RJ45 Ethernet
2. Login 192.168.8.1 with root password "superzxmn" (SSH Port 22, Telnet Port 5188)
3. Download openwrt firmware on the computer.
4. Use scp or sftp put firmware to board /tmp
5. Use command "mtd -r write openwrt-ramips-mt76x8-hongdian_h7920-v40-squashfs-sysupgrade.bin firmware"
to flash
Original Firmware Dump / More details:
https://blog.gov.cooking/archives/research-hongdian-h7920-v40-and-flash.html
Signed-off-by: Coia Prant <coiaprant@gmail.com>
Tested-by: Coia Prant <coiaprant@gmail.com>
Link: https://github.com/openwrt/openwrt/pull/17726
Signed-off-by: Hauke Mehrtens <hauke@hauke-m.de>
CreatLentem CLT-R30B1 is a wireless WiFi 6 router.
This device uses the CLT-R30B1_0824_V1.1 board
shared by EDUP RT2980, Dragonglass DXG21,
and other diamond-shaped 5-antenna routers.
Specification
-------------
- SoC : MediaTek MT7981B dual-core ARM Cortex-A53 1.3 GHz
- RAM : DDR3 256 MiB
- Flash : SPI-NAND 128 MiB (ESMT F50L1G41LB)
- WLAN : MediaTek MT7976CN dual-band WiFi 6
- 2.4 GHz : b/g/n/ax, MU-MIMO (2x 5 dBi antennas)
- 5 GHz : a/n/ac/ax, MU-MIMO (3x 5 dBi antennas)
- Ethernet :
- LAN x3 : 10/100/1000 Mbps (MediaTek MT7531AE)
- WAN x1 : 10/100/1000 Mbps (MT7981 internal PHY)
- UART : through-hole on PCB
- assignment : (RX), (TX), (GND), [3.3V]
- settings : 115200n8
- Buttons x2 : Mesh/WPS, Reset
- LEDs x2 : Status (Red, Green)
- Power : 12 VDC, 1 A, 2.1*5.5 mm
Important notes
---------------
The device is supplied in two variants.
The main difference is the size of the mtd5 (ubi)
partition in the flash layout: 64M or 112M.
112M version: Has ImmortalWrt firmware installed with LuCI WebUI.
64M version: Has stock firmware based on OpenWrt,
with the WaveLink/GL.iNet WebUI and older U-Boot
compared to the 112M version.
Flash instructions for 112M version
-----------------------------------
Follow the standard OpenWrt sysupgrade procedure without saving data.
Use the clt-r30b1-112m-squashfs-sysupgrade.bin image.
All checks should pass - don't proceed if a "not supported"
warning is issued.
Flash instructions for 64M version
----------------------------------
WebUI Method:
1. Prepare the upgrade image with clt-r30b1-squashfs-sysupgrade.bin
using the script: make_staged_upgrade_tar.sh
or use the prepared image: staged_openwrt_upgrade.bin
Downloaded from:
https://github.com/andros-ua/owrt-misc/tree/main/clt-r30b1
2. Install the prepared image using the stock WebUI update page.
3. Press and hold the reset button after reboot
to wipe the stock config and gain access.
SSH Method:
1. Connect via SSH using dg:ivanlee credentials.
2. Upload the clt-r30b1-squashfs-sysupgrade.bin image.
3. Use the command: sysupgrade -n
All checks should pass - don't proceed if a "not supported"
warning is issued.
Return to stock
---------------
Flash a backup of the ubi mtdblock (mtd5)
using the OpenWrt sysupgrade method.
Recovery
--------
Both variants:
Connect UART and use the U-Boot menu to flash the firmware image
or boot an OpenWrt initramfs image.
112M with newer U-Boot:
Power on the router while pressing the mesh button for 3 seconds.
The U-Boot Flash WebUI will be available at http://192.168.1.1
MAC Addresses:
-------------------------------------------------------
| Interface | MAC | Source |
---------------|-------------------|-------------------
| LAN | B4:4D:43:D1:xx:xx | Factory, 0x2A |
| WAN | B4:4D:43:D1:xx:xx | Factory, 0x24 |
| WLAN 2.4 GHz | B4:4D:43:D2:xx:xx | Factory, 0x4 |
| WLAN 5 GHz | B4:4D:43:D2:xx:xx | Factory, 0x4 + 1 |
-------------------------------------------------------
Signed-off-by: Andrii Kuiukoff <andros.ua@gmail.com>
Link: https://github.com/openwrt/openwrt/pull/19534
Signed-off-by: Hauke Mehrtens <hauke@hauke-m.de>
The current variables tagged_ports and untagged_ports suggest that
these are distinct and describe only the ports in each of these
configuration types.
That is wrong. The hardware is configured via member ports and
untagged ports. The first one being a superset of the second.
Rename the variables to reflect that.
Signed-off-by: Markus Stockhausen <markus.stockhausen@gmx.de>
Link: https://github.com/openwrt/openwrt/pull/19684
Signed-off-by: Hauke Mehrtens <hauke@hauke-m.de>
Both RTL930x and RTL931x were missing the code to support enabling and
disabling MAC address learning and unknown unicast flooding on a per-port
basis.
* rtl93*x_enable_learning() allows toggling of dynamic MAC learning on
individual ports by modifying the L2 learning constraint control
register.
* rtl93*x_enable_flood() provides the ability to control unknown unicast
flooding behavior, disabling forwarding when set. If it is enabled, it
will just forward it. If it is disabled, packets will simply be dropped.
Signed-off-by: Harshal Gohel <hg@simonwunderlich.de>
Signed-off-by: Sharadanand Karanjkar <sk@simonwunderlich.de>
Link: https://github.com/openwrt/openwrt/pull/19581
Signed-off-by: Hauke Mehrtens <hauke@hauke-m.de>
Hardware
--------
- SOC: MediaTek MT7981B
- RAM: 256MB DDR3
- FLASH: 128MB SPI-NAND WinBond W25N01GVZEIG
- NETWORK: 2x1Gb Lan 1x1Gb Wan
- WIFI: MediaTek MT7981B 2x2 DBDC 802.11ax 2T2R (2.4/5)
- LEDs: 3x WAN/LAN (green) 2x STATUS (red/blue)
- USB: 1x XHCI
Installation via Webinterface
-----------------------------
1. Rename OpenWrt sysupgrade bin to wavlink_wl-wn551X3-squashfs-sysupgrade.bin
The uppercase chars 551X3 are essential and checked by web interface.
2. Logon to webinterface
3. Go to network configuration -> mode selection
4. Choose mode "LAN bridge/access point"
5. Save configuration (maybe network reconfig needed)
6. Go to system upgrade
7. Choose local upgrade and provide renamed sysupgrade file
8. Start upgrade and wait for completion
9. Logon to OpenWrt (network config is preserved during upgrade)
Boot initramfs via TFTP & console
---------------------------------
1. Connect switch to network via LAN1 or LAN2
2. Power on switch
3. Press ESC until prompt reached "MT7981>"
4. Set own IP "setenv ipaddr 192.168.x.y"
5. Set TFTP IP "setenv serverip 192.168.a.b"
6. Set memory address "setenv loadaddr 0x46000000"
7. Download image "tftpboot openwrt-mediatek-filogic-wavlink_wl-wn551x3-initramfs.itb"
8. Boot image "bootm"
Notes
-----
- The red/blue LEDs give a background illumination to the top of the
case. The red LED is totally disabled to avoid noisy blinking.
- Aside from the design and the different LED colors & placements
the hardware and partitioning matches the WAVLINK WL-WN586X3 Rev B.
Therefor a common DTSI was prepared.
MAC Addresses (same as stock)
-----------------------------
LAN : 80:3F:5D:xx:xx:B1 (hw, 0x44e(text))
WAN : 80:3F:5D:xx:xx:B2 (hw, 0x460(text))
2.4GHz: 80:3F:5D:xx:xx:B1 (Factory, 0x4 (hex))
5GHz : driver auto generated
Signed-off-by: Markus Stockhausen <markus.stockhausen@gmx.de>
Link: https://github.com/openwrt/openwrt/pull/19515
Signed-off-by: Hauke Mehrtens <hauke@hauke-m.de>
Define MSM430 as alternative name, to explicitly show the device is
supported using existing image (MSM460).
I can confirm that the guide from
https://github.com/blocktrron/msm460-flashing works perfectly fine with
the HP MSM430 as well.
In fact, the MSM430 running the original firmware operates as
a 2x3:2 access point, but after flashing it with OpenWRT, it functions
as a 3x3:3 access point — just like the MSM460 model.
It seems that the MSM430 is essentially the same hardware as the MSM460,
with limitations imposed by the original (HP) software.
Signed-off-by: Jan Taczanowski <jan.taczanowski@gmail.com>
Link: https://github.com/openwrt/openwrt/pull/19540
Signed-off-by: Hauke Mehrtens <hauke@hauke-m.de>
This commit adds support for a dual-band AC1200 wall plug
manufactured by Shenzhen Century Xinyang Tech Co., Ltd.
SoC: Mediatek MT7628AN (MIPS 24KEc single core, 580 MHz)
RAM: 128 MiB DDR2 (Hynix HY5PS1G1631C)
ROM: 8 MiB SPI NOR (Zbit ZB25VQ64ASIG)
Wired: one FE RJ45 port (+ an unpopulated footprint for a 2nd)
WiFi: Mediatek MT7612E
Ant.: four 2 dBi external antennas (two 2.4GHz, two 5 GHz)
LEDs: - Power (green, always on)
- 2.4G (green, controlled by MT7628)
- 5G (green, controlled by MT7612)
- Extender (green, GPIO 37, used as status LED)
- LAN (green/yellow, controlled by RT3050 ESW)
Buttons: WPS and reset (both connected to GPIO 38)
Power: 5V 2-pin JST-XH on main PCB
110/220V AC to 5V 1.5A DC on auxiliary PCB
UART: 57600 8n1 3.3v, holes available on the PCB as J5
pinout is (Gnd) (Tx) (Rx)
MAC: 1C:BF:CE:xx:xx:xx (2.4 GHz, label)
1C:BF:CE:xx:xx:xx + 1 (LAN)
1C:BF:CE:xx:xx:xx + 2 (WAN, not in use)
1C:BF:CE:xx:xx:xx + 3 (5 GHz)
Original firmware is Chaos Calmer 15.05.01 (kernel 3.10.108)
with a few custom packages and a non-LuCI web interface.
Telnet is enabled, requiring an unknown root password [1].
Root password is also needed to access the router via UART console,
but passwordless telnet can be enabled via a trivial web exploit [2]
and then the root password can be removed by editing `/etc/shadow`.
Installation: Upload `sysupgrade` binary via web interface at
`http://192.168.188.1/settings.shtml`. Alternatively, remove
root password and use u-boot menu to flash image via TFTP.
Notes:
- Device model in Chaos Calmer is "mtk-apsoc-demo".
- It is sold under several brands, e.g., Fenvi and Linkavenir.
It is available in two colors: white and black.
- PCB is marked "WD206AD v1.0".
- Instead of a standard ethernet transformer, the PCB has a few tiny
SMD coils.
- The housing is identical to the one used by a 2020 model,
WD-R1203U, which is RTL8812-based. The older model has an FCC
listing with external and internal images: ZNPWD-R1203U.
The FCC listing contains a letter [3] claiming WD-R1203U and
WD-R1208U are internally identical, but evidently they are not.
[1] root:$1$7rmMiPJj$91iv9LWhfkZE/t7aCBdo.0:18388:0:99999:7:::
This is the same hash as in Wodesys WD-R1802U.
There are other root password hashes in `/etc/shadow_sf` and
`/etc/shadow_yn`.
[2] curl -X POST http://192.168.188.1/cgi-bin/adm.cgi \
-d page=Lang -d langType="en;killall telnetd;telnetd -l /bin/sh"
[3] https://fcc.report/FCC-ID/ZNPWD-R1203U/4767033
Signed-off-by: Rani Hod <rani.hod@gmail.com>
Link: https://github.com/openwrt/openwrt/pull/19535
Signed-off-by: Hauke Mehrtens <hauke@hauke-m.de>
mach-rtl83xx.h contained the required register definitions for older SoC
families but was missing it for RTL930x and RTL931x.
Signed-off-by: Harshal Gohel <hg@simonwunderlich.de>
Signed-off-by: Sharadanand Karanjkar <sk@simonwunderlich.de>
Link: https://github.com/openwrt/openwrt/pull/19574
Signed-off-by: Hauke Mehrtens <hauke@hauke-m.de>
Each MBR ctrl block has 64 bits to store the 56 possible ports. The offsets
between the groups is therefore also 64 bit.
Signed-off-by: Sven Eckelmann <sven@narfation.org>
Signed-off-by: Sharadanand Karanjkar <sk@simonwunderlich.de>
Link: https://github.com/openwrt/openwrt/pull/19574
Signed-off-by: Hauke Mehrtens <hauke@hauke-m.de>
The comment incorrectly stated that RTL931X doesn't have smi_poll_ctrl. But
there is actually a register for using it.
Signed-off-by: Harshal Gohel <hg@simonwunderlich.de>
Signed-off-by: Sharadanand Karanjkar <sk@simonwunderlich.de>
Link: https://github.com/openwrt/openwrt/pull/19574
Signed-off-by: Hauke Mehrtens <hauke@hauke-m.de>
Some of the parameters added to RTL9300_FAMILY_ID are missing for
RTL9310_FAMILY_ID. Simply add the missing ones to keep sharing code between
the two SoCs.
Signed-off-by: Harshal Gohel <hg@simonwunderlich.de>
Signed-off-by: Sharadanand Karanjkar <sk@simonwunderlich.de>
Link: https://github.com/openwrt/openwrt/pull/19574
Signed-off-by: Hauke Mehrtens <hauke@hauke-m.de>
* In RTL931x, bit 31 of the (4th column) of 802_1Q_VLAN_QINQ table
indicates the validity of l2 tunnel. Before bit 63 (3rd column)
was being checked for validity of l2 tunnel.
* The untagged_ports requires 64 bits to represent 56 ports. Do not
store u64 in u32 variable
* First 24 ports are represented in the 2nd register not just first 20
Signed-off-by: Harshal Gohel <hg@simonwunderlich.de>
Signed-off-by: Sharadanand Karanjkar <sk@simonwunderlich.de>
Link: https://github.com/openwrt/openwrt/pull/19576
Signed-off-by: Hauke Mehrtens <hauke@hauke-m.de>
OpenFi 6C is a portable Wi-Fi 6 travel router based on MediaTek MT7981B+MT7976CN.
Two slightly different versions have been sold. The V1 board has a green color and lacks the modem LED. The V2 board is black and has a LED for the modem. The firmware should work on both of them.
Specifications:
- SoC: MediaTek MT7981B (Filogic 820) 1.3GHz dual-core ARM Cortex-A53
- RAM: 1GB DDR4
- Flash: 256MB SPI NAND
- Wireless: 2.4GHz/5GHz 802.11ax
- Ethernet: 1x 10/100/1000M LAN
- USB: 1x USB 3.0 Type-A port
- Expansion: M.2 slot for 5G modem
- Cooling: PWM-controlled fan
- Buttons: Reset, Mode switch
- LEDs: System, Ethernet, 5G WiFi, Modem status
**Installation via U-Boot web page**
1. Set static IP 192.168.21.2/255.255.255.0 on your computer.
2. Connect to the Ethernet port and hold the reset button while booting the device. Wait for 6-8 seconds, and release the reset button.
3. Open U-boot web page on your browser at http://192.168.21.1
4. Select the OpenWRT sysupgrade image, upload it, and start the upgrade.
5. Wait for automatic reboot.
**Installation via sysupgrade**
Flash the sysupgrade file via LuCI upgrade page without saving the settings.
Signed-off-by: Jiasheng Zhu <newbanyaya@gmail.com>
Link: https://github.com/openwrt/openwrt/pull/19512
Signed-off-by: Hauke Mehrtens <hauke@hauke-m.de>
SIM SIMAX1800U has the similar hardware design as the SIMAX1800T. The
only difference is the Ethernet portmap.
Specification
-------------
- SoC : Mediatek MT7621
- RAM : 256 MiB DDR3
- Flash : 128 MiB NAND Flash
- WLAN : Mediatek MT7905 DBDC
- 2.4 GHz : 2x2 MIMO WiFi6
- 5 GHz : 2x2 MIMO WiFi6
- Ethernet : MT7621 built-in 10/100/1000 Mbps 1x WAN; 3x LAN
- UART : 3.3V, 115200n8
- Buttons : 1x RESET; 1x WPS/MESH
- LEDs : 1x Multi-Color(Blue;Green;Red)
- Power : DC 12V1A
- CMIIT ID : 2022AP7163
- TFTP IP :
- server : 192.168.1.254
- router : 192.168.1.28
TFTP Installation(recommend)
------------
1. Set local tftp server IP "192.168.1.254" and NetMask "255.255.255.0".
2. Rename initramfs-kernel.bin to "factory.bin" and put it in the root
directory of the tftp server. tftpd64 is a good choice for Windows.
3. Remove all Ethernet cables and WiFi connections from the PC, except
for the one connected to the SIMAX1800U. Start the TFTP server, plug
in the power adapter and wait for the OpenWrt system to boot.
4. Backup "firmware" partition and rename it to "firmware.bin". We need
it to back to the stock firmware.
5. Use "fw_printenv" command to list envs. If "firmware_select=2" is
observed then set u-boot env variable via command:
`fw_setenv firmware_select 1`
6. Apply sysupgrade.bin in OpenWrt LuCI.
Web UI Installation
------------
1. Apply update by uploading initramfs-factory.bin to the web UI.
2. Use "fw_printenv" command to list envs. If "firmware_select=2" is
observed then set u-boot env variable via command:
`fw_setenv firmware_select 1`
3. Apply squashfs-sysupgrade.bin in OpenWrt LuCI.
Return to Stock Firmware
----------------------------
Restore the backup firmware partition in the installation step 4.
MAC addresses
-------------
+---------+-------------------+
| | MAC example |
+---------+-------------------+
| LABEL | 98:xx:xx:xx:xx:b2 |
| LAN | 98:xx:xx:xx:xx:b5 |
| WAN | 98:xx:xx:xx:xx:b2 |
| WLAN2G | 98:xx:xx:xx:xx:b4 |
| WLAN5G | 9a:xx:xx:xx:xx:b4 |
+---------+-------------------+
Tips:
-----------
User can use `TFTP Installation` method to recover a brick device.
Signed-off-by: Shiji Yang <yangshiji66@outlook.com>
Link: https://github.com/openwrt/openwrt/pull/19455
Signed-off-by: Hauke Mehrtens <hauke@hauke-m.de>
The vendor DTS defined incorrect GPIOs for the LEDs, which caused them
to not function properly. Initially, the WAN, WLAN LEDs appeared to
work, but further testing showed that they were non-functional.
This patch corrects the GPIO assignments in the DTS, restoring full LED
functionality including blinking, except the power LED which cannot be
software controlled.
Tested on a CF-EW71 v2 unit.
Fixes: ee3a6adc6c ("ath79: add support for Comfast CF-EW71 v2")
Signed-off-by: Felix Golatofski <git@xdfr.de>
Link: https://github.com/openwrt/openwrt/pull/19665
Signed-off-by: Hauke Mehrtens <hauke@hauke-m.de>
The workqueue items don't need to be processed directly when they are
scheduled. It can happen that they are simply processed at a much later
time. It is therefore necessary to ensure that all workqueue items of a
driver are no longer being processed before the driver (or structures of
this driver) are destroyed.
When skipping this step, the driver driver can cause a kernel Oops on
reboot.
Unfortunately, it is not recommended [1] to flush items out of the system
workqueue - simply because this can cause deadlocks. The driver itself must
have a private workqueue which is then flushed.
[1] https://lkml.kernel.org/r/49925af7-78a8-a3dd-bce6-cfc02e1a9236@I-love.SAKURA.ne.jp
Signed-off-by: Issam Hamdi <ih@simonwunderlich.de>
Signed-off-by: Harshal Gohel <hg@simonwunderlich.de>
Signed-off-by: Sharadanand Karanjkar <sk@simonwunderlich.de>
Link: https://github.com/openwrt/openwrt/pull/19570
Signed-off-by: Hauke Mehrtens <hauke@hauke-m.de>
Just like rtl930x, rtl931x also requires two reads to fetch current link
status.
While at it, rename the function to a proper naming scheme.
Signed-off-by: Harshal Gohel <hg@simonwunderlich.de>
Co-developed-by: Markus Stockhausen <markus.stockhausen@gmx.de>
Signed-off-by: Markus Stockhausen <markus.stockhausen@gmx.de>
Co-developed-by: Sven Eckelmann <sven@narfation.org>
Signed-off-by: Sven Eckelmann <sven@narfation.org>
Signed-off-by: Sharadanand Karanjkar <sk@simonwunderlich.de>
Link: https://github.com/openwrt/openwrt/pull/19578
Signed-off-by: Hauke Mehrtens <hauke@hauke-m.de>
Link status needs to be read twice, and a single register value is
enough for determining link status for all the ports
It is not necessary to go through each potential port separately and later
actually identify for which ports the interrupt actually was. The helper
for_each_set_bit() directly iterate through all set bits.
While at it, rename the function to a proper naming scheme.
Signed-off-by: Harshal Gohel <hg@simonwunderlich.de>
Co-developed-by: Markus Stockhausen <markus.stockhausen@gmx.de>
Signed-off-by: Markus Stockhausen <markus.stockhausen@gmx.de>
Signed-off-by: Sharadanand Karanjkar <sk@simonwunderlich.de>
Link: https://github.com/openwrt/openwrt/pull/19578
Signed-off-by: Hauke Mehrtens <hauke@hauke-m.de>
Currently the SerDes driven SFP ports give strange ethtool readings
on RTL93xx devices. Especially duplex and speed are shown even if
no link is up and running. That leads to confusion because the MAC
reports arbitrary values.
Enhance the readout by refactoring the pcs_get_state() function.
Calculate speed/duplex/pause only if link is detected.
Suggested-by: Markus Stockhausen <markus.stockhausen@gmx.de>
Signed-off-by: Harshal Gohel <hg@simonwunderlich.de>
Signed-off-by: Sharadanand Karanjkar <sk@simonwunderlich.de>
Link: https://github.com/openwrt/openwrt/pull/19575
Signed-off-by: Hauke Mehrtens <hauke@hauke-m.de>
The media_sts register only shows type of link, fiber/copper,
and has nothing to do with the link status
Signed-off-by: Harshal Gohel <hg@simonwunderlich.de>
Signed-off-by: Sharadanand Karanjkar <sk@simonwunderlich.de>
Link: https://github.com/openwrt/openwrt/pull/19575
Signed-off-by: Hauke Mehrtens <hauke@hauke-m.de>
Sophos XG 210r3 is a rackmounted x86 based firewall with 6 RJ-45 gigabit
ethernet ports (eth0-5) and 2 SFP gigabit ethernet ports (eth6, eth7)
all running Intel NICs supported by igb driver. This board update maps
eth0 (left most RJ-45 port) as wan and eth1-7 as lan.
Signed-off-by: Steve Wavler <trenchcoatjedi@gmail.com>
Link: https://github.com/openwrt/openwrt/pull/19647
Signed-off-by: Hauke Mehrtens <hauke@hauke-m.de>
We are slowly getting to the point where the mdio driver will be
carved out from the ethernet driver. Since the beginning it had
the feature to hand out SFP serdes as phys. So one can access
them from the phy driver. This will be kept during the final
migration and it even will provide a consistent interface for the
phy/serdes registers.
With this being done we need to identify how to handle the affected
ports in a generic way for all targets. Doing first things first,
this starts with a consistent DTS. Currently we have:
for RTL838x + Zyxel XGS1210:
phy-mode = "1000base-x"
managed = "in-band-status"
phy-handle = ...
for all other RTL93x devices:
phy-mode = "10gbase-r"
managed = "in-band-status"
pseudo-phy-handle = ...
Looking at the phylink kernel code one can see a nifty detail.
There is dynamic phy bringup depending on the mode.
int phylink_fwnode_phy_connect(struct phylink *pl,
const struct fwnode_handle *fwnode,
u32 flags)
{
struct fwnode_handle *phy_fwnode;
struct phy_device *phy_dev;
int ret;
/* Fixed links and 802.3z are handled without needing a PHY */
if (pl->cfg_link_an_mode == MLO_AN_FIXED ||
(pl->cfg_link_an_mode == MLO_AN_INBAND &&
phy_interface_mode_is_8023z(pl->link_interface)))
return 0;
...
}
Where 802.3z means 1000base-x or 2500base-x. Aligning this with
IEEE specs it means essentially:
- 10gbase-r defined ports with phy-handle must statically bring up
a phylink from the beginning that immediately depends on a
phy read_status() implementation.
- 1000base-x/2500base-x defined ports will dynamically bringup a
phylink during link detection regardless of a phy-handle. So
it usually runs at the moment when a SFP has been plugged in.
We currently still rely on a phy-handle but do not want to bring
up the phy immediately. Commit 4457c1eee4 ("realtek: rtl93xx:
support SFPs with phys") tried to fix exactly that error for
10gbase-r definied ports. Kernel shows "sfp sfp-p8: sfp_add_phy
failed: -EBUSY" in that case.
But it did it in the wrong way. It implemented a workaround by
introducing a DTS property "pseudo-phy-handle". Instead it
should have simply converted the DTS nodes to 1000base-x.
Revert the commit and fix the DTS with wrong definitions. From
now on we have a consistent SFP definition throughout all DTS
and targets.
Aside from the positive effect this setting has it is more or
less an arbitrary speed definition. When plugging in the SFP the
real speed will be choosen dynamically.
Fixes: 4457c1eee4 ("realtek: rtl93xx: support SFPs with phys")
Tested-By: Bjørn Mork <bjorn@mork.no>
Signed-off-by: Markus Stockhausen <markus.stockhausen@gmx.de>
Link: https://github.com/openwrt/openwrt/pull/19648
Signed-off-by: Hauke Mehrtens <hauke@hauke-m.de>
Patches 12 and 13 have been superseded by patch 12. Other patches
have no significant changes.
Signed-off-by: Aleksander Jan Bajkowski <olek2@wp.pl>
Link: https://github.com/openwrt/openwrt/pull/19675
Signed-off-by: Hauke Mehrtens <hauke@hauke-m.de>
Userspace handling of both calibration and mac addresses is deprecated.
Also fixed calibration size for ath9k. AR9287 uses 3d8 for its size.
Signed-off-by: Rosen Penev <rosenp@gmail.com>
Link: https://github.com/openwrt/openwrt/pull/17289
Signed-off-by: Robert Marko <robimarko@gmail.com>
The current build recipe creates a lzma based initramfs and
a gzip based sysupgrade (installation) image. No need to
use different compression methods. Use lzma for both.
Tested-by: Andrew LaMarche <andrewjlamarche@gmail.com>
Signed-off-by: Markus Stockhausen <markus.stockhausen@gmx.de>
Link: https://github.com/openwrt/openwrt/pull/19669
Signed-off-by: Robert Marko <robimarko@gmail.com>
Add SoC revision, CPU part number, and a flag for engineering samples to
the rtl83xx_soc_info structure.
Also extend the system type string to include this information.
Signed-off-by: Jan Hoffmann <jan@3e8.eu>
Link: https://github.com/openwrt/openwrt/pull/19653
Signed-off-by: Robert Marko <robimarko@gmail.com>
Move the definitions to mach-rtl83xx.h, so they can be used during init
to read more detailed SoC information. Also rename the RTL931X register,
as it has the same address on all RTL93xx.
Signed-off-by: Jan Hoffmann <jan@3e8.eu>
Link: https://github.com/openwrt/openwrt/pull/19653
Signed-off-by: Robert Marko <robimarko@gmail.com>
Read model name from the register instead of using hard-coded values.
Also remove detection of the unsupported Realtek ESW/SSW SoCs. The Fast
Ethernet variants of the Maple and Cypress series stay for now, but are
moved to the RTL8380/RTL8390 families.
Signed-off-by: Jan Hoffmann <jan@3e8.eu>
Link: https://github.com/openwrt/openwrt/pull/19653
Signed-off-by: Robert Marko <robimarko@gmail.com>
Use the lzma recipe for the device for both initramfs and sysupgrade to
save some flash space due to smaller image. U-Boot build on this device
has native lzma support.
Signed-off-by: Jonas Jelonek <jelonek.jonas@gmail.com>
Link: https://github.com/openwrt/openwrt/pull/19657
Signed-off-by: Robert Marko <robimarko@gmail.com>
The migration of the RTL930x mdio/serdes access functions over to the
mdio bus is a little more complicated than for RTL83xx. There are several
places where the serdes is accessed directly. So do it in two steps. With
this first step:
- use the rtmdio prefix for the serdes reader/writer functions
- move the functions over to the bus (inside the ethernet driver)
- Adapt all callers.
This is not only a copy/paste but the serdes access will be hardened too.
For this:
- put a mutex around the read/write functions because we have only
indirect register access through a mdio style bus.
- Verify input values to avoid data mess.
Tested-by: Bjørn Mork <bjorn@mork.no>
Tested-by: Jan Hoffmann <jan@3e8.eu>
Tested-by: Jonas Jelonek <jelonek.jonas@gmail.com>
Signed-off-by: Markus Stockhausen <markus.stockhausen@gmx.de>
Link: https://github.com/openwrt/openwrt/pull/19662
Signed-off-by: Robert Marko <robimarko@gmail.com>
Since 6.12 is now default, drop 6.6 support.
Signed-off-by: Aleksander Jan Bajkowski <olek2@wp.pl>
Link: https://github.com/openwrt/openwrt/pull/19682
Signed-off-by: Nick Hainke <vincent@systemli.org>
Let's switch the lantiq target to use kernel 6.12 by default.
Signed-off-by: Aleksander Jan Bajkowski <olek2@wp.pl>
Link: https://github.com/openwrt/openwrt/pull/19682
Signed-off-by: Nick Hainke <vincent@systemli.org>
Update default kernel version to 6.12 and drop configs and patches for
kernel 6.6.
Signed-off-by: Stefan Kalscheuer <stefan@stklcode.de>
Link: https://github.com/openwrt/openwrt/pull/19666
Signed-off-by: Nick Hainke <vincent@systemli.org>
Like RTL839x the RTL930x SoCs have multithreading built in.
Activate it in the kernel configuration.
Signed-off-by: Markus Stockhausen <markus.stockhausen@gmx.de>
Link: https://github.com/openwrt/openwrt/pull/19624
Signed-off-by: Robert Marko <robimarko@gmail.com>
The RTL839x mdio functions are scattered around the code. Relocate
them to the bus (still inside the ethernet driver).
Additionally provide a consistent SerDes register access through the
mdio bus. Until now when a SerDes directly drives a SFP module there
is no clear rule of how to handle its register set that consists of
two parts:
- c22 phy registers 0-15 live in the fiber page (2) of the SerDes
- other SerDes specific registers exist in pages before and after
The mdio bus and other SerDes functions are a wild mix of directly
looking into page 2 or just using self defined methods to access
data.
Adapt the bus to the new consistent phy interface that mixes the
SerDes register set like classic Realtek phys do it.
- Use register 31 as page select (already in the bus)
- Always keep the common registers 0-15 in place and read fiber page
- Map the SerDes internal registers into the upper vendor specific
registers 16-23 according to the page select register (31).
That gives a register mapping as follows:
+-----------------------+-----------------------+---------------+-------------+
| reg 0x00-0x0f | reg 0x10-0x17 | reg 0x18-0x1e | reg 0x1f |
+-----------------------+-----------------------+---------------+-------------+
| SerDes fiber page (3) | real SerDes registers | zero | SerDes page |
| registers 0 - 15 | in packages of 8 | | select reg |
+-----------------------+-----------------------+---------------+-------------+
Example to make it as clear as possible.
SerDes registers on a RTL839x show
Page / Reg | 0x00 0x01 0x02 0x03 0x04 0x05 0x06 0x07 0x08 0x09 0x0A 0x0B ...
-------------+----------------------------------------------------------------
0 - SDS | 0C03 0F00 7060 7106 074D 0EBF 0F0F 0359 5248 0000 0F80 0000 ...
1 - SDS_EXT | 0000 0000 85FA 8C6D 5CCC 0000 20D8 0003 79AA 8C64 00C3 1482 ...
2 - FIB | 1140 6189 001C CA40 01A0 0000 0000 0004 0000 0000 0000 0000 ...
3 - FIB_EXT | 1140 6109 001C CA40 01A0 0000 0000 0004 0000 0000 0000 0000 ...
This translates to this phy layout
| SerDes fiber registers normal SerDes registers zero p.sel
Page / Reg | 0x00 0x01 0x02 0x03 ... 0x10 0x11 0x12 0x13 ... 0x18 ... 0x1f
-------------+---------------------------------------------------------------
0 | 1140 6189 001C CA40 ... 0C03 0F00 7060 7106 ... 0000 ... 0000
1 | 1140 6189 001C CA40 ... 5248 0000 0F80 0000 ... 0000 ... 0001
...
4 | 1140 6189 001C CA40 ... 0000 0000 85FA 8C6D ... 0000 ... 0004
...
Signed-off-by: Markus Stockhausen <markus.stockhausen@gmx.de>
Link: https://github.com/openwrt/openwrt/pull/19634
Signed-off-by: Robert Marko <robimarko@gmail.com>
* Use SDS for phy 48/49
* Use correct link/phy settings for SFP ports
* Remove read-only flag from u-boot env so fw_setenv actually works
Signed-off-by: Joe Holden <jwh@zorins.us>
Link: https://github.com/openwrt/openwrt/pull/19596
Signed-off-by: Hauke Mehrtens <hauke@hauke-m.de>
When a SerDes directly drives a SFP module there is no clear rule of
how to handle its register set that consists of two parts:
- c22 phy registers 0-15 live in the fiber page (2) of the SerDes
- other SerDes specific registers exist in pages before and after
The mdio bus and other SerDes functions are a wild mix of directly
looking into page 2 or just using self defined methods to access
data.
Provide a consistent phy interface that mixes the SerDes register
set like classic Realtek phys do it.
- Use register 31 as page select (already in the bus)
- Always keep the common registers 0-15 in place and read fiber page
- Map the SerDes internal registers into the upper vendor specific
registers 16-23 according to the page select register (31).
That gives a register mapping as follows:
+-----------------------+-----------------------+---------------+-------------+
| reg 0x00-0x0f | reg 0x10-0x17 | reg 0x18-0x1e | reg 0x1f |
+-----------------------+-----------------------+---------------+-------------+
| SerDes fiber page (3) | real SerDes registers | zero | SerDes page |
| registers 0 - 15 | in packages of 8 | | select reg |
+-----------------------+-----------------------+---------------+-------------+
Example to make it as clear as possible.
SerDes registers on a RTL838x show
Page / Reg | 0x00 0x01 0x02 0x03 0x04 0x05 0x06 0x07 0x08 0x09 0x0A 0x0B ...
-------------+----------------------------------------------------------------
0 - SDS | 0C03 0F00 7060 7106 074D 0EBF 0F0F 0359 5248 0000 0F80 0000 ...
1 - SDS_EXT | 0000 0000 85FA 8C6D 5CCC 0000 20D8 0003 79AA 8C64 00C3 1482 ...
2 - FIB | 1140 6189 001C CA40 01A0 0000 0000 0004 0000 0000 0000 0000 ...
3 - FIB_EXT | 1140 6109 001C CA40 01A0 0000 0000 0004 0000 0000 0000 0000 ...
This translates to this phy layout
| SerDes fiber registers normal SerDes registers zero p.sel
Page / Reg | 0x00 0x01 0x02 0x03 ... 0x10 0x11 0x12 0x13 ... 0x18 ... 0x1f
-------------+---------------------------------------------------------------
0 | 1140 6189 001C CA40 ... 0C03 0F00 7060 7106 ... 0000 ... 0000
1 | 1140 6189 001C CA40 ... 5248 0000 0F80 0000 ... 0000 ... 0001
...
4 | 1140 6189 001C CA40 ... 0000 0000 85FA 8C6D ... 0000 ... 0004
For now just do it for RTL838x devices.
Signed-off-by: Markus Stockhausen <markus.stockhausen@gmx.de>
Link: https://github.com/openwrt/openwrt/pull/19604
Signed-off-by: Robert Marko <robimarko@gmail.com>
There is a variant of the Radxa ROCK Pi E v3 equipped with the Realtek
RTL8821CU. Add the kmod-rtw88-8821cu package for it.
Signed-off-by: FUKAUMI Naoki <naoki@radxa.com>
Link: https://github.com/openwrt/openwrt/pull/18310
Signed-off-by: Stijn Tintel <stijn@linux-ipv6.be>
The DSA has a link to the MDIO bus and already uses the read/write functions
that are provided. In parallel the dsa_switch_ops structure provides an
interface for phy_read and phy_write. These are still open-coded and sadly
circumvent the bus. Simplify the implementation and avoid inconsistencies by
reusing the existing bus infrastructure.
Additionally, remove two unused MMD header definitions as a quick win.
Reported-by: Jan Hoffmann <jan@3e8.eu>
Signed-off-by: Markus Stockhausen <markus.stockhausen@gmx.de>
Link: https://github.com/openwrt/openwrt/pull/19548
Signed-off-by: Robert Marko <robimarko@gmail.com>
The function rtl93xx_setup() is called by both RTL930x and RTL931x. But
only the RTL930x specific function to print port matrix was called.
Unfortuntaly, RTL931x needs a different function to access the correct
registers to retrieve the port matrix information.
It is therefore necessary differentiate in rtl93xx_setup between the
SoC families before calling the appropriate function.
Signed-off-by: Harshal Gohel <hg@simonwunderlich.de>
Signed-off-by: Sharadanand Karanjkar <sk@simonwunderlich.de>
Link: https://github.com/openwrt/openwrt/pull/19572
Signed-off-by: Robert Marko <robimarko@gmail.com>
The RTL931x has 56 (0-55) non-CPU ports. To receive updates about the port
state, it is therefore necessary to enable the interrupts for all these
ports.
Signed-off-by: Harshal Gohel <hg@simonwunderlich.de>
Signed-off-by: Sharadanand Karanjkar <sk@simonwunderlich.de>
Link: https://github.com/openwrt/openwrt/pull/19572
Signed-off-by: Robert Marko <robimarko@gmail.com>
* traffic isolation tables are different between rtl930x and rtl931x
* traffic_enable/disable/get/set functions span multiple columns in the
rtl931x as a result, previous implementation would only enable traffic
in some ports.
traffic_enable/disable and traffic_set/get should now work on all ports and
not just the initial 32
Signed-off-by: Harshal Gohel <hg@simonwunderlich.de>
Signed-off-by: Sharadanand Karanjkar <sk@simonwunderlich.de>
Link: https://github.com/openwrt/openwrt/pull/19572
Signed-off-by: Robert Marko <robimarko@gmail.com>
A commit which broke netdev trigger LEDs offloaded to PHYs recently made
it all the way down to the Linux 6.6 stable branch. The revert has been
accepted to linux-next, however, a backport to the various -stable trees
is still pending.
Import the backported revert commit to fix in OpenWrt in the meantime
until the revert also gets picked to linux-stable.
Link: https://git.kernel.org/pub/scm/linux/kernel/git/next/linux-next.git/commit/?id=26f732791f2bcab18f59c61915bbe35225f30136
Signed-off-by: Daniel Golle <daniel@makrotopia.org>
Deleted useless content, since it is the same as the mainline kernel
Signed-off-by: Coia Prant <coiaprant@gmail.com>
Link: https://github.com/openwrt/openwrt/pull/19300
Signed-off-by: Robert Marko <robimarko@gmail.com>
Remove extra blank lines.
Fixes typo for label and status.
Signed-off-by: Chukun Pan <amadeus@jmu.edu.cn>
Link: https://github.com/openwrt/openwrt/pull/19400
Signed-off-by: Robert Marko <robimarko@gmail.com>
Include the NAND specs into the DTS. It is unclear which devices
really need it. Keep it disabled for now. As the SoC register area
is defined too small until now, increase the size to an appropriate
value.
If enabled one can see the following log messages (e.g. Linksys
LGS328C or LGS352C).
[ 1.206600] spi-nand spi1.0: Macronix SPI NAND was found.
[ 1.212795] spi-nand spi1.0: 128 MiB, block size: 128 KiB, page size: 2048, OOB size: 64
[ 1.222217] 3 fixed-partitions partitions found on MTD device spi1.0
[ 1.229466] OF: Bad cell count for /soc/spi@1a400/flash@0/partitions
[ 1.236617] OF: Bad cell count for /soc/spi@1a400/flash@0/partitions
[ 1.244164] Creating 3 MTD partitions on "spi1.0":
[ 1.249620] 0x000000000000-0x000004000000 : "ubifs"
[ 1.423593] 0x000004000000-0x000005e00000 : "firmware"
[ 1.738268] mtdsplit_uimage: no uImage found in "firmware"
[ 1.744577] 0x000005e00000-0x000007c00000 : "runtime2"
Signed-off-by: Markus Stockhausen <markus.stockhausen@gmx.de>
Link: https://github.com/openwrt/openwrt/pull/19583
Signed-off-by: Robert Marko <robimarko@gmail.com>
RTL93xx devices have a NAND controller built in. Upstream already
has a driver in place. Include it downstream. Activate it in the
RTL93xx builds and disable it for the RTL83xx builds.
Signed-off-by: Markus Stockhausen <markus.stockhausen@gmx.de>
Link: https://github.com/openwrt/openwrt/pull/19583
Signed-off-by: Robert Marko <robimarko@gmail.com>
During PHY matching, the SMI polling must be disabled to avoid conflicts
during the complex detection routine. Only after this finished, SMI polling
is allowed again.
This was implemented for all realtek families besides RTL931x.
Signed-off-by: Harshal Gohel <hg@simonwunderlich.de>
Signed-off-by: Sharadanand Karanjkar <sk@simonwunderlich.de>
Link: https://github.com/openwrt/openwrt/pull/19603
Signed-off-by: Robert Marko <robimarko@gmail.com>
A RTL930x function to read the value from an SDS register must not used on
an RTL931x SoC. Doing it with rtl930x_read_sds_phy() would corrupt the
written results when only parts of the bits are written.
Fixes: 7026084066 ("realtek: Add SDS configuration routines for the RTL93XX platforms")
Signed-off-by: Harshal Gohel <hg@simonwunderlich.de>
Signed-off-by: Sharadanand Karanjkar <sk@simonwunderlich.de>
Link: https://github.com/openwrt/openwrt/pull/19603
Signed-off-by: Robert Marko <robimarko@gmail.com>
Vimin VM-S100-0800MS is an 8 port Multi-Gig switch, based on RTL9303.
Ported from XikeStor SKS8300-8X with changes to support different u-boot
build.
Specification:
- SoC : Realtek RTL9303
- RAM : DDR3 512 MiB
- Flash : SPI-NOR 16 MiB (Winbond W25Q128JVSQ)
- Ethernet : 8x 1/2.5/10 Gbps (SFP+)
- LEDs/Keys (GPIO): 0x/1x
- UART : "Console" port on the front panel
- type : RS-232C
- connector : RJ-45
- settings : 115200n8
- Power : AC100-240V 50/60Hz
Flash instruction using initramfs image:
1. Prepare TFTP server with an IP address "192.168.1.111"
2. Connect your PC to Port1 on VM-S100-0800MS
3. Power on VM-S100-0800MS and interrupt boot by pressing Esc
4. Enable Port1 with the following commands
rtk 10g 0 fiber1g (or fiber10g if 10GBase-*R, dac300cm for DAC cable)
rtk ext-devInit 0
rtk ext-pinSet 2 0
Note: the last command sets tx-disable to low
7. Download initramfs image from TFTP server
tftpboot 0x82000000 <image name>
8. Boot with the downloaded image
bootm
9. On the initramfs image, backup the stock firmware if needed
10. Upload (or download) sysupgrade image to the device
11. Erase "firmware" partition to cleanup JFFS2 of stock FW
mtd erase firmware
12. Perform sysupgrade with the sysupgrade image
13. Wait ~120 sec to complete flashing
Reverting to stock firmware:
1. Prepare by downloading the stock firmware. Vimin doesn't have
the firmware on their website, tested using firmware for shared
hardware Nicgiga S100-0800S-M.
Filename: vmlinux-nicgiga-S100-0800S-M-241126EN.bix
2. Prepare TFTP server with an IP address "192.168.1.111"
3. Connect your PC to Port1 on VM-S100-0800MS
4. Power on VM-S100-0800MS and interrupt boot by pressing Esc
5. Enable Port1 with the following commands
rtk 10g 0 fiber1g (or fiber10g if 10GBase-*R, dac300cm for DAC cable)
rtk ext-devInit 0
rtk ext-pinSet 2 0
Note: the last command sets tx-disable to low
6. Download initramfs image from TFTP server
tftpboot 0x82000000 <image name>
7. Boot with the downloaded image
bootm
8. Under Management -> Firmware -> Upgrade/Backup, upload bix file.
9. Reboot device
Signed-off-by: Colton Pawielski <cepawiel@mtu.edu>
Link: https://github.com/openwrt/openwrt/pull/19477
Signed-off-by: Hauke Mehrtens <hauke@hauke-m.de>
The tsens node had an extra space in the "okay" status string, preventing
thermal sensors from being properly registered. This patch corrects it to
enable proper thermal monitoring support.
Signed-off-by: Shubham Vishwakarma <shubhamvis98@fossfrog.in>
Link: https://github.com/openwrt/openwrt/pull/19564
Signed-off-by: Robert Marko <robimarko@gmail.com>
This commit adds support for Hasivo S1100W-8XGT-SE switch.
Device specification
--------------------
SoC Type: RTL9303
RAM: Samsung K4B461646E-BYKO (512MB)
Flash: Fudan FM25Q128A (16 MB)
Ethernet: 8x 10G via 2x RTL8264 PHY
LEDs: 2 LEDs, 1 power green, 1 system green
Button: Reset
USB ports: None
Bootloader: Realtek U-Boot - U-Boot 2011.12.(3.6.6.55087) (Nov 13 2022 - 14:37:31)
Fan: 2 fans controlled by STC8G1K08 TSOP-20 microcontroller
Note: The fan appears to operate the same irrespective of the running
firmware. The STC9G1K08 is likely operating independently.
To explore the stock vendor firmware, there are 2 avenues to gain root
access. This is not necessary to install OpenWrt, but is here for
reference.
Root access via serial
----------------------
1. ctrl+t
2. password: switchrtk
3. press 's' for shell
Root access via SSH
-------------------
1. ctrl+t
2. password: switchrtk
3. sys command sh
4. log in with your username+password
5. ctrl+t
6. password: switchrtk
7. press 's' for shell
Credit to https://forum.openwrt.org/t/hasivo-switches/151758/174 for rooting instructions.
Installing OpenWrt
------------------
1. Connect to UART. UART requires soldering an RJ45 connector to the
console footprint on the board. The header is on the top right of
this image: 4d2ab97fad.jpeg
2. Set computer IP to 192.168.0.111.
3. Enter bootloader by pressing esc key during boot.
4. Enter password 'Hs2021cfgmg'.
5. Type 'XXXX'.
6. setenv bootcmd 'rtk network on; bootm 0xb4300000'
7. saveenv
8. rtk network on
9. tftpboot 0x84f00000 <openwrt-initramfs>
10. bootm 0x84f00000
Now you can copy over the sysupgrade image and install.
Credit to
https://forum.openwrt.org/t/hasivo-switches/151758/22?u=andrewjlamarche
for u-boot console access instructions.
Signed-off-by: Andrew LaMarche <andrewjlamarche@gmail.com>
Link: https://github.com/openwrt/openwrt/pull/17137
Signed-off-by: Hauke Mehrtens <hauke@hauke-m.de>
Since Linux 6.7, introduced with commit 5c2f7727d437 ("mtd: mtdpart:
check for subpartitions parsing result"), errors during subpartition
parsing cause all MTD partitions to be torn down.
Since the current mtdsplit driver for devices using H3C VFS returns
-EINVAL if it does not find a file system containing an OpenWrt image,
this makes initial installation of OpenWrt impossible.
Work around this by returning 0 when the file system contains unexpected
data. Also print a message in this case to show what is going on.
Signed-off-by: Jan Hoffmann <jan@3e8.eu>
Link: https://github.com/openwrt/openwrt/pull/19475
Signed-off-by: Hauke Mehrtens <hauke@hauke-m.de>
Adds the capability to flash the factory image using the OEM recovery
software, ipTIME Firmware Wizard(11ac).
Installation
------------
1. Download the OEM recovery software from the manufacturer's website
2. Download the *squashfs-factory.bin file from the OpenWrt website
3. Press a reset button, and power up the router(keep pressing the reset button)
4. Wait more than 10 seconds until the CPU LED stop blinking
5. Connect the router(LAN port) to the PC
6. Run the OEM recovery software and follow the instructions
7. Select the *squashfs-factory.bin file during the router recovery process
8. Wait for the router to boot from *squashfs-factory.bin
Signed-off-by: Donghyun Ko <nyankosoftware@gmail.com>
Link: https://github.com/openwrt/openwrt/pull/19497
Signed-off-by: Hauke Mehrtens <hauke@hauke-m.de>
Maintain 64 bit counters by polling the hardware counters and adding up
the differences. Polling needs to happen just often enough to catch
every single overflow.
As we now have non-overflowing counters now, we can safely calculate
composite counters without getting weird results on overflow. Use this
to follow RFC 3635 more accurately by mapping the hardware counters to
the proper counters, while taking into account hardware quirks as best
as possible.
Signed-off-by: Jan Hoffmann <jan@3e8.eu>
Link: https://github.com/openwrt/openwrt/pull/18415
Signed-off-by: Hauke Mehrtens <hauke@hauke-m.de>
By default, the network interface stats are based on software counters,
which only consider traffic from and to the CPU. Implementing the
get_stats64 method allows to report the full hardware counters instead.
Signed-off-by: Jan Hoffmann <jan@3e8.eu>
Link: https://github.com/openwrt/openwrt/pull/18415
Signed-off-by: Hauke Mehrtens <hauke@hauke-m.de>
The kernel offers several alternatives to get_ethtool_stats which allow
to report some stats in a more structured way. Use them where possible.
Ideally, we should follow RFC 3635 to translate the hardware counters to
the supported frame and octet counters. However, this is not feasible,
as some of the counters are 32-bit only (so it would produce incorrect
results as soon as one of them overflows).
Signed-off-by: Jan Hoffmann <jan@3e8.eu>
Link: https://github.com/openwrt/openwrt/pull/18415
Signed-off-by: Hauke Mehrtens <hauke@hauke-m.de>
The MIB registers contain different stats depending on the SoC, and for
RTL930x some stats are in an additional register.
Create separate MIB descs for each SoC to implement this. Also make
reading 64-bit counters more robust, by protecting against an overflow
of the lower 32 bits during the read.
RTL931x remains unsupported, because it uses a table and thus requires
a separate implementation.
While we are at it, rename structs/functions to use the rtldsa prefix.
Signed-off-by: Jan Hoffmann <jan@3e8.eu>
Link: https://github.com/openwrt/openwrt/pull/18415
Signed-off-by: Hauke Mehrtens <hauke@hauke-m.de>
kmod-md-multipath was removed in kernel 6.12, remove the dependency here
too.
This fixes the build of the gemini target.
Fixes: d12a603de5 ("kernel: kmod-md-multipath: Depend on kernel 6.6")
Link: https://github.com/openwrt/openwrt/pull/19532
Signed-off-by: Hauke Mehrtens <hauke@hauke-m.de>
After observation that timer interrupt 7 always fires on secondary VPEs
the counter was disabled in the startup code. This is a bad idea when
building the kernel with jitterentropy. To generate entropy it makes use
of function random_get_entropy(). On MIPS architecture this simply reads
the counter register on the current core. With a disabled counter it
always returns the same value and the entropy initialization stalls the
core if it runs on a secondary VPE. See backtrace
[ 21.736246] rcu: INFO: rcu_sched self-detected stall on CPU
[ 21.736246] rcu: INFO: rcu_sched self-detected stall on CPU
[ 21.748594] rcu: 1-....: (2100 ticks this GP) idle=064c/1/0x40000002 softirq=7/7 fqs=1050
[ 21.748594] rcu: 1-....: (2100 ticks this GP) idle=064c/1/0x40000002 softirq=7/7 fqs=1050
[ 21.766871] rcu: (t=2102 jiffies g=-1187 q=25 ncpus=2)
[ 21.766871] rcu: (t=2102 jiffies g=-1187 q=25 ncpus=2)
[ 21.778429] CPU: 1 UID: 0 PID: 1 Comm: swapper/0 Not tainted 6.12.39 #482
[ 21.778429] CPU: 1 UID: 0 PID: 1 Comm: swapper/0 Not tainted 6.12.39 #482
[ 21.778461] Hardware name: Zyxel GS1900-48
[ 21.778461] Hardware name: Zyxel GS1900-48
...
[ 21.779757] [<8029b968>] jent_measure_jitter+0xc8/0x10c
[ 21.779757] [<8029b968>] jent_measure_jitter+0xc8/0x10c
[ 21.779779] [<8029b9e8>] jent_gen_entropy+0x3c/0xb0
[ 21.779779] [<8029b9e8>] jent_gen_entropy+0x3c/0xb0
[ 21.779800] [<8029bcc0>] jent_entropy_collector_alloc+0x104/0x118
[ 21.779800] [<8029bcc0>] jent_entropy_collector_alloc+0x104/0x118
[ 21.779822] [<8029bd6c>] jent_entropy_init+0x4c/0x2ec
[ 21.779822] [<8029bd6c>] jent_entropy_init+0x4c/0x2ec
[ 21.779844] [<8086f184>] jent_mod_init+0x58/0xac
[ 21.779844] [<8086f184>] jent_mod_init+0x58/0xac
[ 21.779865] [<80100200>] do_one_initcall+0x70/0x250
[ 21.779865] [<80100200>] do_one_initcall+0x70/0x250
[ 21.779883] [<8085c018>] kernel_init_freeable+0x1f0/0x280
[ 21.779883] [<8085c018>] kernel_init_freeable+0x1f0/0x280
[ 21.779905] [<8067cba4>] kernel_init+0x20/0xb0
[ 21.779905] [<8067cba4>] kernel_init+0x20/0xb0
[ 21.779926] [<80101158>] ret_from_kernel_thread+0x14/0x1c
[ 21.779926] [<80101158>] ret_from_kernel_thread+0x14/0x1c
This bit of entropy is helpful on these low end devices. Reenable the
counter and simply disable the interrupt.
Fixes: b7aab19585 ("realtek: SMP handling of R4K timer interrupts")
Reported-by: Sebastian Gottschall <s.gottschall@dd-wrt.com>
Signed-off-by: Markus Stockhausen <markus.stockhausen@gmx.de>
Link: https://github.com/openwrt/openwrt/pull/19499
Signed-off-by: Hauke Mehrtens <hauke@hauke-m.de>
The mdio bus functions are still split between ethernet and dsa driver.
Before moving everthing out to a separate mdio driver we decided to
collect everything in the ethernet driver with the rtmdio prefix.
Take over the remaining RTL838x functions.
Remark: This is more or less a copy/paste with function renaming. As
there are still some consumers in the DSA driver the definitions and
inclusions must be flipped.
Signed-off-by: Markus Stockhausen <markus.stockhausen@gmx.de>
Link: https://github.com/openwrt/openwrt/pull/19484
Signed-off-by: Hauke Mehrtens <hauke@hauke-m.de>
Currently the SerDes driven SFP ports give strange ethtool readings
on RTL83xx devices. Especially duplex and speed are shown even if
no link is up and running. That leads to confusion because the MAC
reports arbitrary values.
Enhance the readout by refactoring the pcs_get_state() function.
Calculate speed/duplex/pause only if link is detected. Additionally
add reporting of 10G for SFP+ on RTL839x.
ethtool for empty SFP cage before/after
root@OpenWrt:~# ethtool lan9
Settings for lan9:
Supported ports: [ MII ]
Supported link modes: 1000baseT/Full
1000baseKX/Full
1000baseX/Full
1000baseT1/Full
Supported pause frame use: Symmetric Receive-only
Supports auto-negotiation: Yes
Supported FEC modes: Not reported
Advertised link modes: 1000baseT/Full
1000baseKX/Full
1000baseX/Full
1000baseT1/Full
Advertised pause frame use: Symmetric Receive-only
Advertised auto-negotiation: Yes
Advertised FEC modes: Not reported
Speed: 10Mb/s
Duplex: Half
Port: MII
PHYAD: 0
Transceiver: internal
Auto-negotiation: on
Supports Wake-on: d
Wake-on: d
Link detected: no
root@OpenWrt:~# ethtool lan9
Settings for lan9:
Supported ports: [ MII ]
Supported link modes: 1000baseT/Full
1000baseKX/Full
1000baseX/Full
1000baseT1/Full
Supported pause frame use: Symmetric Receive-only
Supports auto-negotiation: Yes
Supported FEC modes: Not reported
Advertised link modes: 1000baseT/Full
1000baseKX/Full
1000baseX/Full
1000baseT1/Full
Advertised pause frame use: Symmetric Receive-only
Advertised auto-negotiation: Yes
Advertised FEC modes: Not reported
Speed: Unknown!
Duplex: Unknown! (255)
Port: MII
PHYAD: 0
Transceiver: internal
Auto-negotiation: on
Supports Wake-on: d
Wake-on: d
Link detected: no
ethtool with inserted but NOT connected 1G module before/after
root@OpenWrt:~# ethtool lan9
Settings for lan9:
Supported ports: [ FIBRE ]
Supported link modes: 1000baseX/Full
Supported pause frame use: Symmetric Receive-only
Supports auto-negotiation: Yes
Supported FEC modes: Not reported
Advertised link modes: 1000baseX/Full
Advertised pause frame use: Symmetric Receive-only
Advertised auto-negotiation: Yes
Advertised FEC modes: Not reported
Speed: 1000Mb/s
Duplex: Full
Port: FIBRE
PHYAD: 0
Transceiver: internal
Auto-negotiation: on
Supports Wake-on: d
Wake-on: d
Link detected: no
root@OpenWrt:~# ethtool lan9
Settings for lan9:
Supported ports: [ FIBRE ]
Supported link modes: 1000baseX/Full
Supported pause frame use: Symmetric Receive-only
Supports auto-negotiation: Yes
Supported FEC modes: Not reported
Advertised link modes: 1000baseX/Full
Advertised pause frame use: Symmetric Receive-only
Advertised auto-negotiation: Yes
Advertised FEC modes: Not reported
Speed: Unknown!
Duplex: Unknown! (255)
Port: FIBRE
PHYAD: 0
Transceiver: internal
Auto-negotiation: on
Supports Wake-on: d
Wake-on: d
Link detected: no
Signed-off-by: Markus Stockhausen <markus.stockhausen@gmx.de>
Link: https://github.com/openwrt/openwrt/pull/19524
Signed-off-by: Robert Marko <robimarko@gmail.com>
This allows building the kmod-drm-ivpu which depends on
CONFIG_DRM_ACCEL. This module is x86_64 only.
Link: https://github.com/openwrt/openwrt/pull/19480
Signed-off-by: Hauke Mehrtens <hauke@hauke-m.de>
The kmod-rpi-panel-attiny-regulator and kmod-rpi-panel-7inch-touchscreen
are included in target modules.mk file, they should also depend on the target,
otherwise they can be selected from every target.
Fix the AutoProbe for panel-raspberrypi-touchscreen too.
Link: https://github.com/openwrt/openwrt/pull/19480
Signed-off-by: Hauke Mehrtens <hauke@hauke-m.de>
The kmod-imx2-wdt, kmod-imx7-ulp-wdt and kmod-wdt-sp805 are included in
target modules.mk file, they should also depend on the target, otherwise
they can be selected from every target.
Link: https://github.com/openwrt/openwrt/pull/19480
Signed-off-by: Hauke Mehrtens <hauke@hauke-m.de>
The kmod-ata-dwc is included in target modules.mk file, it should also
depend on the target, otherwise it can be selected from every target.
Link: https://github.com/openwrt/openwrt/pull/19480
Signed-off-by: Hauke Mehrtens <hauke@hauke-m.de>
The CONFIG_BCMGENET kernel config option will select this driver. Add
the driver to the kernel config menu and make kmod-bcmgenet depend on
it.
Link: https://github.com/openwrt/openwrt/pull/19480
Signed-off-by: Hauke Mehrtens <hauke@hauke-m.de>
The SerDes setup function needs to be called to make 2500Base-X work.
Signed-off-by: Jan Hoffmann <jan@3e8.eu>
Link: https://github.com/openwrt/openwrt/pull/19517
Signed-off-by: Hauke Mehrtens <hauke@hauke-m.de>
On some devices (like ZyXEL GS1920) the phys are not initialized and patched
by the bootloader. This is done through the vendor SDK when the software
starts. To make these devices usable too, provide the most basic setup
sequence for the RTL8218B.
Signed-off-by: Markus Stockhausen <markus.stockhausen@gmx.de>
Link: https://github.com/openwrt/openwrt/pull/19491
Signed-off-by: Hauke Mehrtens <hauke@hauke-m.de>
The driver currently uses two checks to verify the capabilities. These
are ..._phylink_get_caps() and ..._pcs_validate(). For RTL930x these
must allow 2.5G modes. Enhance that as follows:
Add 2500BASEX to phylink_get_caps(). Sort the interfaces alphabetically
and rename the function to the new prefix. IMPORTANT REMARK! Until now
this function allowed the XGMII mode (10G only parallel interface) that
was somehow mixed with the Realtek proprietary mode XSGMII (10G SGMII).
Remove it to avoid further confusion.
Looking upstream pcs_validate() is used less and less. There are only
2 consumers left in 6.16 and the calling location reads:
/* Validate the link parameters with the PCS */
if (pcs->ops->pcs_validate) {
ret = pcs->ops->pcs_validate(pcs, supported, state);
if (ret < 0 || phylink_is_empty_linkmode(supported))
return -EINVAL;
/* Ensure the advertising mask is a subset of the
* supported mask.
*/
linkmode_and(state->advertising, state->advertising,
supported);
}
There is no need for this additional check. Drop the functions.
Tested-by: Jan Hoffmann <jan@3e8.eu>
Signed-off-by: Markus Stockhausen <markus.stockhausen@gmx.de>
Link: https://github.com/openwrt/openwrt/pull/19429
Signed-off-by: Hauke Mehrtens <hauke@hauke-m.de>
This file should be generated automatically at runtime by the kernel
build system.
Link: https://github.com/openwrt/openwrt/pull/19473
Signed-off-by: Hauke Mehrtens <hauke@hauke-m.de>
Fix bootloop on TP-Link EAP615-Wall v1 by reducing LZMA dictionary
size. Before this patch and after an upgrade to kernel 6.12 this
device couldn't boot a kernel because of an error: "lzma compressed:
uncompress error 1".
I have chosen -d22 as dictionary size as suggested by @namiltd.
The usual sizes for problematic devices are -d16, -d20, -d22. I
have confirmed with my tests that this device can boot with a value
up to -d27, but there is no size benefit from values above -d21,
therefore -d22 is good enough.
See also: https://github.com/openwrt/openwrt/issues/19403
Signed-off-by: Marcin FM <marcin@ipv8.pl>
Link: https://github.com/openwrt/openwrt/pull/19433
Signed-off-by: Hauke Mehrtens <hauke@hauke-m.de>
Specification
-------------
- SoC : MediaTek MT7981BA dual-core ARM Cortex-A53 1.3GHz
- RAM : DDR3 256Mbytes, ESMT M15T2G16128A
- Flash : 128Mbytes NAND Flash, ESMT F50L1G41LB
- WLAN : MediaTek MT7976CN dual-band Wi-Fi 6
- 2.4GHz : b/g/n/ax, MU-MIMO
- 5GHz : a/n/ac/ax, MU-MIMO
- Ethernet : MediaTek MT7531AE
- LAN : 10/100/1000 Mbps x4
- WAN : 10/100/1000 Mbps x1
- UART : 1x4 pin header on PCB
- [J6] TX, RX, GND, 3.3V (115200, 8N1)
- Buttons : WPS, Reset
- LEDs : 1x CPU (Amber)
1x Wi-Fi 5GHz (Amber)
1x Wi-Fi 2.4GHz (Amber)
1x WAN activity (Amber)
4x LAN activity (Amber)
- Power : 12VDC, 1A (Center positive polarity)
MAC address
-----------
+-----------+-------------------+-----------------------+
| Interface | MAC | Algorithm |
+-----------+-------------------+-----------------------+
| WLAN 2.4G | B0:38:6C:48:xx:xx | label |
| WLAN 5G | B2:38:6C:48:xx:xx | label with LA Bit Set |
| WAN | B0:38:6C:48:xx:xx | label + 1 |
| LAN | B0:38:6C:48:xx:xx | label + 3 |
+-----------+-------------------+-----------------------+
The WLAN 2.4G MAC was found in 'Factory' partition, 0x4
Installation
------------
1. Download the OEM recovery software from the manufacturer's website
2. Download the *squashfs-factory.bin file from the OpenWrt website
3. Press a reset button, and power up the router(keep pressing the reset button)
4. Wait more than 10 seconds until the CPU LED stop blinking
5. Connect the router(LAN port) to the PC
6. Replace a file in the OEM recovery software with the file from step 2
7. Run the OEM recovery software and follow the instructions
8. Wait for the router to boot from *squashfs-factory.bin
Signed-off-by: Donghyun Ko <nyankosoftware@gmail.com>
Link: https://github.com/openwrt/openwrt/pull/19368
Signed-off-by: Hauke Mehrtens <hauke@hauke-m.de>
Some NanoPC-T6 boards with A3A444 eMMC chips experience I/O errors and
corruption when using HS400 mode. Downgrade to HS200 mode to ensure
stable operation.
Fixes: #18844
Signed-off-by: Grzegorz Sterniczuk <grzegorz@sternicz.uk>
Link: https://github.com/openwrt/openwrt/pull/19398
[Add patch header]
Signed-off-by: Hauke Mehrtens <hauke@hauke-m.de>
This commit increases the SPI bus frequency from 20 to 52 MHz. Reduces boot
time by 2s. Below is a performance comparison.
Before:
root@OpenWrt:~# dd if=/dev/mtd5 of=/dev/null bs=10M count=1 status=progress
10485760 bytes (10 MB, 10 MiB) copied, 2 s, 5.8 MB/
After:
root@OpenWrt:~# dd if=/dev/mtd5 of=/dev/null bs=10M count=1 status=progress
10485760 bytes (10 MB, 10 MiB) copied, 1 s, 9.7 MB/s
Taken from PR #18752 as each device should be tested individually, so I have
created a separate PR for this.
Signed-off-by: Sky Huang <SkyLake.Huang@mediatek.com>
Signed-off-by: Aleksander Jan Bajkowski <olek2@wp.pl>
Link: https://github.com/openwrt/openwrt/pull/19439
Signed-off-by: Hauke Mehrtens <hauke@hauke-m.de>
With the switch to Linux 6.12 this driver was enabled by accident.
However, it doesn't support any of the router SoCs but is meant to be
used only by the smartphone, tablet and chromebook SoCs.
Disable the driver again to silence a kernel error logline during boot.
Fixes: 0a0f5f94ec ("mediatek: mt7623: update config-6.12")
Fixes: 029b7ed9c4 ("mediatek: mt7622: update config-6.12")
Reported-by: https://aparcar.org/openwrt-tests/119/
Signed-off-by: Daniel Golle <daniel@makrotopia.org>
Add new mtdsplit parser "mstc-boot" for the devices manufactured by MSTC
(Mitra Star Technology Corp.). This is necessary to handle dual-boot on
those devices.
This parser splits kernel+rootfs or only rootfs(or UBI) based on the
image in the firmware partition or pre-defined partitions in dts, and
"bootnum" value in the "persist" (or "working") partition.
Note: "bootnum" is used for switching active firmware partitions on the
devices manufactured by MSTC and '1' or '2' are used on most
devices. But some devices use '0' or '1'. (example: I-O DATA
WN-DEAX1800GR)
Sequence:
1. obtain "bootnum" value
2. child nodes exsist (regardless of bootnum)
-> fixed partitions
(active parts : without bootnum (ex.: "kernel", "rootfs")
inactive parts: with bootnum (ex.: "kernel2", "rootfs2"))
3. current partition is active (dt bootnum == mtd bootnum)
-> image-based partitions
Device Tree:
- common
- mstc,bootnum : "bootnum" value for the mtd partition (0/1/2)
- mstc,persist : phandle of "persist" partition containing "bootnum"
value
- fixed partitions
- #address-cells: indicate cell count of address of child nodes (1)
- #size-cells : indicate cell count of size of child nodes (1)
- (child nodes) : define the child partitions
- reg : define the offset and size
- label-base : define the base name of the partition
- (example) : base:"kernel"->"kernel"(active)/"kernel2"(inactive)
example:
partition@3c0000 {
compatible = "mstc,boot";
reg = <0x3c0000 0x3240000>;
label = "firmware1";
mstc,bootnum = <1>;
mstc,persist = <&mtd_persist>;
#address-cells = <1>;
#size-cells = <1>;
partition@0 {
reg = <0x0 0x800000>;
label-base = "kernel";
};
partition@800000 {
reg = <0x800000 0x2a40000>;
label-base = "ubi";
};
};
- image-based partitions
(no additional properties)
example:
partition@5a0000 {
compatible = "mstc,boot";
label = "firmware1";
reg = <0x5a0000 0x3200000>;
mstc,bootnum = <1>;
mstc,persist = <&mtd_persist>;
};
Signed-off-by: INAGAKI Hiroshi <musashino.open@gmail.com>
Link: https://github.com/openwrt/openwrt/pull/18976
Signed-off-by: Hauke Mehrtens <hauke@hauke-m.de>
The 6.12 testing kernel for ipq40xx target is ready now.
Tested on SKSpruce WIA3300-20.
Signed-off-by: Shiji Yang <yangshiji66@outlook.com>
Link: https://github.com/openwrt/openwrt/pull/18725
Signed-off-by: Hauke Mehrtens <hauke@hauke-m.de>
On the ipq40xx platform, the bus range is 1 - 255. Therefore, bus
number 0 is clearly incorrect. Change the bus number to 1, just
like other ipq40xx devices. This patch fixes the following dtc
warnings on 6.12 kernel:
qcom-ipq4019.dtsi:476.5-29: Warning (pci_device_bus_num): /soc/pcie@40000000/pcie@0/wifi@0,0:bus-range: PCI bus number 0 out of range, expected (1 - 255)
qcom-ipq4019.dtsi:476.5-29: Warning (pci_device_bus_num): /soc/pcie@40000000/pcie@0/wifi@0,0:bus-range: PCI bus number 0 out of range, expected (1 - 255)
Signed-off-by: Shiji Yang <yangshiji66@outlook.com>
Link: https://github.com/openwrt/openwrt/pull/18725
Signed-off-by: Hauke Mehrtens <hauke@hauke-m.de>
- Remove duplicate PCIe bridge. A default bridge node has been
added upstream.
- Do not refer to the qca807x node. This node label has been
removed. We can disable the qca807x phy in mdio node.
Signed-off-by: Shiji Yang <yangshiji66@outlook.com>
Link: https://github.com/openwrt/openwrt/pull/18725
Signed-off-by: Hauke Mehrtens <hauke@hauke-m.de>
Add a bridge node label so that we can insert PCIe peripheral nodes.
Signed-off-by: Shiji Yang <yangshiji66@outlook.com>
Link: https://github.com/openwrt/openwrt/pull/18725
Signed-off-by: Hauke Mehrtens <hauke@hauke-m.de>
Copy arch directory from 6.12 kernel to restore the default
6.6 device tree files.
Signed-off-by: Shiji Yang <yangshiji66@outlook.com>
Link: https://github.com/openwrt/openwrt/pull/18725
Signed-off-by: Hauke Mehrtens <hauke@hauke-m.de>
Copy patches and kernel configs from 6.12 kernel to restore the
default 6.6 kernel support files.
Signed-off-by: Shiji Yang <yangshiji66@outlook.com>
Link: https://github.com/openwrt/openwrt/pull/18725
Signed-off-by: Hauke Mehrtens <hauke@hauke-m.de>
This is a preparation for 6.12 kernel support. It can help us
track the device tree files history by using the Git tool.
Signed-off-by: Shiji Yang <yangshiji66@outlook.com>
Link: https://github.com/openwrt/openwrt/pull/18725
Signed-off-by: Hauke Mehrtens <hauke@hauke-m.de>
This is a preparation for 6.12 kernel support. It can help us
track the patches and Kconfig history by using the Git tool.
Signed-off-by: Shiji Yang <yangshiji66@outlook.com>
Link: https://github.com/openwrt/openwrt/pull/18725
Signed-off-by: Hauke Mehrtens <hauke@hauke-m.de>
This is a preparation for introducing the 6.12 kernel support.
All configs are automatically refreshed. In theory, they will
generate the same .config files in the kernel build directory
as before.
Signed-off-by: Shiji Yang <yangshiji66@outlook.com>
Link: https://github.com/openwrt/openwrt/pull/18725
Signed-off-by: Hauke Mehrtens <hauke@hauke-m.de>
The prototype of `devm_platform_ioremap_resource_byname()` was defined
in `linux/platform_device.h`.
Signed-off-by: Shiji Yang <yangshiji66@outlook.com>
Link: https://github.com/openwrt/openwrt/pull/18725
Signed-off-by: Hauke Mehrtens <hauke@hauke-m.de>
This function is only used by the current source file gcc-ipq4019.c.
Signed-off-by: Shiji Yang <yangshiji66@outlook.com>
Link: https://github.com/openwrt/openwrt/pull/18725
Signed-off-by: Hauke Mehrtens <hauke@hauke-m.de>
The node name should include the reg property value. Fix warning:
qcom-ipq4019-lbr20.dts:415.17-449.4: Warning (i2c_bus_reg): /soc/i2c@78b7000/led-controller: I2C bus unit address format error, expected "27"
Signed-off-by: Shiji Yang <yangshiji66@outlook.com>
Link: https://github.com/openwrt/openwrt/pull/18725
Signed-off-by: Hauke Mehrtens <hauke@hauke-m.de>
The files-6.6 and files-6.12 folder contain the same content, merge them
into the files folder for both kernel versions.
Link: https://github.com/openwrt/openwrt/pull/19423
Signed-off-by: Hauke Mehrtens <hauke@hauke-m.de>
The ix4-200d is a 4 bay NAS supported since OpenWrt 23.05. Drive trays
controller. Due to a kernel-related issue with the SATA controller,
trays #1 and #2 were not recognized. This issue has been fixed in
kernel 6.10, so with the adoption of kernel 6.12 in the Kirkwood
target trays #1 and #2 can now be made accessible. This requires the
kmod-ata-ahci package, which this commit adds as default to the
makefile.
Signed-off-by: Sander van Deijck <sander@vandeijck.com>
Link: https://github.com/openwrt/openwrt/pull/19435
Signed-off-by: Hauke Mehrtens <hauke@hauke-m.de>
These u-boot images are no longer automatically copied to the
bindir since commit:
ed50004319 ("uboot-mediatek: add support for Linksys E8450")
Signed-off-by: Shiji Yang <yangshiji66@outlook.com>
Package kernel modules for PS/2 mouse support, mostly to allow
using touchpads and trackpoints built-into laptops (many of those
are connected using classic i8052-compatible PS/2 I/O).
Signed-off-by: Daniel Golle <daniel@makrotopia.org>
pci driver went to a different directory and thus manually edited.
All else done with kernel_oldconfig.
Signed-off-by: Rosen Penev <rosenp@gmail.com>
Link: https://github.com/openwrt/openwrt/pull/18798
Signed-off-by: Hauke Mehrtens <hauke@hauke-m.de>
Copy kernel config and patches from 6.12 to restore the default 6.6
kernel support files.
Signed-off-by: Rosen Penev <rosenp@gmail.com>
Link: https://github.com/openwrt/openwrt/pull/18798
Signed-off-by: Hauke Mehrtens <hauke@hauke-m.de>
This is a preparation for 6.12 kernel support. It can help us
track the files history by using the Git tool.
Signed-off-by: Rosen Penev <rosenp@gmail.com>
Link: https://github.com/openwrt/openwrt/pull/18798
Signed-off-by: Hauke Mehrtens <hauke@hauke-m.de>
RTL83xx devices have two types of receive interrupts for each of its
8 rings. One for packet received and another for ring overflow. When
the switch is flooded with incoming packets the receive handler will
disable the packet receive notification but still keeps the overflow
notification enabled. While the receive path "slowly" processes the
received packets each new packet triggers the overflow IRQ again. The
device becomes unresponsive and eventually produces messages like:
[18441.709764] rcu: Stack dump where RCU GP kthread last ran:
[18441.727892] Sending NMI from CPU 1 to CPUs 0:
[18441.742300] NMI backtrace for cpu 0 skipped: idling at 0x8080e994
[18415.251700] rcu: INFO: rcu_sched detected stalls on CPUs/tasks:
[18415.271350] rcu: 0-...!: (0 ticks this GP) idle=d740/0/0x0 ...
[18415.303046] rcu: (detected by 1, t=6004 jiffies, g=230925, ...
[18415.326095] Sending NMI from CPU 1 to CPUs 0:
[18415.340540] NMI backtrace for cpu 0
Fix this issue by always disabling receive and overflow interrupts at
the same time.
Test with hping3 --udp -p 5021 -d 1400 --flood 192.168.2.72
Before (3sec run):
[183260.324846] rtl838x-eth 1b00a300.ethernet eth0: RX buffer overrun: status 0x101, mask: 0x7ffeff
[183260.340524] rtl838x-eth 1b00a300.ethernet eth0: RX buffer overrun: status 0x1, mask: 0x7ffeff
[183260.345799] net_ratelimit: 489997 callbacks suppressed
After (3 sec run):
[ 373.981479] rtl838x-eth 1b00a300.ethernet eth0: rx ring overrun: status 0x101, mask: 0x7fffff
[ 374.031118] rtl838x-eth 1b00a300.ethernet eth0: rx ring overrun: status 0x101, mask: 0x7fffff
[ 377.919996] net_ratelimit: 34 callbacks suppressed
Signed-off-by: Markus Stockhausen <markus.stockhausen@gmx.de>
Link: https://github.com/openwrt/openwrt/pull/19365
Signed-off-by: Hauke Mehrtens <hauke@hauke-m.de>
The current implementation has several issues:
- it uses the hacky phy_port* macros
- it uses SoC dependent raw pages
- it disables/enables SoC dependent polling
Get rid of these dependencies and access the mdio bus the normal way.
Signed-off-by: Markus Stockhausen <markus.stockhausen@gmx.de>
Link: https://github.com/openwrt/openwrt/pull/19372
Signed-off-by: Hauke Mehrtens <hauke@hauke-m.de>
Add an OpenWrt-based U-Boot build for this device, allowing for more
flexibility and customization.
Expected behaviour
------------------
When plugging the device, keeping the reset button pressed will enter
TFTP recovery mode: the board will send requests for the initramfs file
(openwrt-mediatek-filogic-glinet_gl-mt2500-initramfs-kernel.bin) from
IP 192.168.1.1 to 192.168.1.10 TFTP server.
The bootloader will populate the environment with the unit serial number
as reported by the "sn" value in eMMC, the "sn_bak" value, the country
code and ddns. WAN and LAN MAC addresses are reported in the environment
as well.
Limitations
-----------
No web interface is available, and only the LAN port can be used for
system recovery.
Notes
-----
This port has been tested with the Maxlinear version only, and with a
board that does not exhibit eMMC communication problems. Even though eMMC
frequency has been lowered, some testing is probably needed and always
very welcome.
A -factory image has been introduced, and is only needed when using the
"Load Firmware via TFTP then write to eMMC." boot menu function.
The device has not been converted to use uImage.FIT including the rootfs
to keep compatibility with stock bootloader and firmware.
Installation
------------
From a Linux root shell:
0. Transfer the needed files to the board, placing them in /tmp.
1. Make sure your U-Boot environment is erased: all of my units came with
unpopulated environment, but I am not sure this is always the case.
Issue the command
cat /dev/zero >/dev/mmcblk0p2
(you will get a "no space left" error, which is reasonable and expected).
2. Unlock the eMMC boot area where BL2 is located:
echo 0 >/sys/block/mmcblk0boot0/force_ro
3. Write the new BL2 code:
cat openwrt-mediatek-filogic-glinet_gl-mt2500-emmc-preloader.bin >/dev/mmcblk0boot0
4. Write new BL31+U-Boot image:
cat openwrt-mediatek-filogic-glinet_gl-mt2500-emmc-bl31-uboot.fip >/dev/mmcblk0p4
5. Reboot.
Signed-off-by: Enrico Mioso <mrkiko.rs@gmail.com>
The device is equipped with a GPS module, reporting data via /dev/ttyS1.
A TF card reader is also present. Only one of those components can be
used at once, since they share some PINs.
This commit adds two devicetree overlays to allow for the user to select
the desired configuration. Another overlay configuration to allow booting
from SD card is provided.
Signed-off-by: Enrico Mioso <mrkiko.rs@gmail.com>
All kernel symbols are automatically refreshed by
`make kernel_oldconfig CONFIG_TARGET=target` and
`make kernel_oldconfig CONFIG_TARGET=subtarget`.
Signed-off-by: Shiji Yang <yangshiji66@outlook.com>
* Drop obsolete flag I2C_CLASS_SPD. [1]
* Change .remove callback return type to NULL.
* Use strscpy instead of strlcpy.
This patch fixes the following build errors:
drivers/i2c/busses/i2c-lantiq.c:599:41: error: 'I2C_CLASS_SPD' undeclared (first use in this function); did you mean 'I2C_CLASS_HWMON'?
599 | adap->class = I2C_CLASS_HWMON | I2C_CLASS_SPD;
| ^~~~~~~~~~~~~
| I2C_CLASS_HWMON
drivers/i2c/busses/i2c-lantiq.c:600:9: error: implicit declaration of function 'strlcpy'; did you mean 'strncpy'? [-Wimplicit-function-declaration]
600 | strlcpy(adap->name, DRV_NAME "-adapter", sizeof(adap->name));
| ^~~~~~~
| strncpy
drivers/i2c/busses/i2c-lantiq.c:729:19: error: initialization of 'void (*)(struct platform_device *)' from incompatible pointer type 'int (*)(struct platform_device *)' [-Wincompatible-pointer-types]
729 | .remove = ltq_i2c_remove,
|
[1] https://git.kernel.org/pub/scm/linux/kernel/git/stable/linux.git/commit/?h=linux-6.12.y&id=e61bcf42d290e73025bab38e0e55a5586c2d8ad5
Signed-off-by: Shiji Yang <yangshiji66@outlook.com>
This is a preparation for 6.12 kernel support. It can help us
track the files history by using the Git tool.
Signed-off-by: Shiji Yang <yangshiji66@outlook.com>
This is a preparation for introducing the 6.12 kernel support.
All configs are automatically refreshed.
Signed-off-by: Shiji Yang <yangshiji66@outlook.com>
This patch fixes the following build warnings:
arch/mips/lantiq/xway/vmmc.c:31:14: error: no previous prototype for 'ltq_get_mps_ad0_irq' [-Werror=missing-prototypes]
31 | unsigned int ltq_get_mps_ad0_irq(void)
| ^~~~~~~~~~~~~~~~~~~
arch/mips/lantiq/xway/vmmc.c:40:14: error: no previous prototype for 'ltq_get_mps_ad1_irq' [-Werror=missing-prototypes]
40 | unsigned int ltq_get_mps_ad1_irq(void)
| ^~~~~~~~~~~~~~~~~~~
arch/mips/lantiq/xway/vmmc.c:49:14: error: no previous prototype for 'ltq_get_mps_vc_irq' [-Werror=missing-prototypes]
49 | unsigned int ltq_get_mps_vc_irq(int idx)
| ^~~~~~~~~~~~~~~~~~
Signed-off-by: Shiji Yang <yangshiji66@outlook.com>
This patch fixes the following build warnings:
arch/mips/pci/ifxmips_pcie.c:1084:36: error: invalid use of undefined type 'struct platform_device'
1084 | struct device_node *node = pdev->dev.of_node;
| ^~
arch/mips/pci/ifxmips_pcie.c:1204:12: error: no previous prototype for 'ifx_pcie_bios_init' [-Werror=missing-prototypes]
1204 | int __init ifx_pcie_bios_init(void)
| ^~~~~~~~~~~~~~~~~~
Signed-off-by: Shiji Yang <yangshiji66@outlook.com>
This patch fixes the following build warnings:
arch/mips/lantiq/xway/ath5k_eep.c:34:12: error: no previous prototype for 'of_ath5k_eeprom_probe' [-Werror=missing-prototypes]
34 | int __init of_ath5k_eeprom_probe(struct platform_device *pdev)
| ^~~~~~~~~~~~~~~~~~~~~
arch/mips/lantiq/xway/eth_mac.c:15:11: error: no previous prototype for 'ltq_get_eth_mac' [-Werror=missing-prototypes]
15 | const u8* ltq_get_eth_mac(void)
| ^~~~~~~~~~~~~~~
Signed-off-by: Shiji Yang <yangshiji66@outlook.com>
This patch fixes the following build warnings:
arch/mips/lantiq/xway/timer.c:160:14: error: no previous prototype for 'ltq_get_fpi_bus_clock' [-Werror=missing-prototypes]
160 | unsigned int ltq_get_fpi_bus_clock(int fpi) {
| ^~~~~~~~~~~~~~~~~~~~~
arch/mips/lantiq/xway/timer.c:803:36: error: invalid use of undefined type 'struct platform_device'
803 | ret = devm_mutex_init(&pdev->dev, &timer_dev.gptu_mutex);
| ^~
arch/mips/lantiq/xway/timer.c:864:12: error: no previous prototype for 'lq_gptu_init' [-Werror=missing-prototypes]
864 | int __init lq_gptu_init(void)
| ^~~~~~~~~~~~
arch/mips/lantiq/xway/timer.c:873:13: error: no previous prototype for 'lq_gptu_exit' [-Werror=missing-prototypes]
873 | void __exit lq_gptu_exit(void)
| ^~~~~~~~~~~~
Signed-off-by: Shiji Yang <yangshiji66@outlook.com>
Add WED related nodes to the device tree of the MT7988 SoC family.
Signed-off-by: Lorenzo Bianconi <lorenzo@kernel.org>
Signed-off-by: Daniel Golle <daniel@makrotopia.org>
Import patches from kernel 6.13:
- net: dsa: realtek: Use for_each_child_of_node_scoped()
- net: dsa: realtek: rtl8365mb: Make use of irq_get_trigger_type()
- net: dsa: realtek: rtl8366rb: Make use of irq_get_trigger_type()
Signed-off-by: Mieczyslaw Nalewaj <namiltd@yahoo.com>
Link: https://github.com/openwrt/openwrt/pull/19381
Signed-off-by: Hauke Mehrtens <hauke@hauke-m.de>
Add driver packages for Intel Low-Power Subsystem devices which are part
of some Intel chipsets. They are mainly needed to have access to the I2C
bus used for HID devices.
Signed-off-by: Daniel Golle <daniel@makrotopia.org>
The current offset used for extracting QCN6122 calibration data
is incorrect on the Yuncore AX830. This patch corrects the
offset to ensure proper WiFi initialization.
Tested on: Yuncore AX830
Signed-off-by: Shubham Vishwakarma <shubhamvis98@fossfrog.in>
Link: https://github.com/openwrt/openwrt/pull/19416
Signed-off-by: Robert Marko <robimarko@gmail.com>
Support for 6.12 is ready; add it as a testing kernel.
Signed-off-by: Pawel Dembicki <paweldembicki@gmail.com>
Link: https://github.com/openwrt/openwrt/pull/19069
Signed-off-by: Hauke Mehrtens <hauke@hauke-m.de>
Most of them were manually refreshed.
Signed-off-by: Pawel Dembicki <paweldembicki@gmail.com>
Link: https://github.com/openwrt/openwrt/pull/19069
Signed-off-by: Hauke Mehrtens <hauke@hauke-m.de>
No need to keep it in kernel specified folder anymore.
Signed-off-by: Pawel Dembicki <paweldembicki@gmail.com>
Link: https://github.com/openwrt/openwrt/pull/19069
Signed-off-by: Hauke Mehrtens <hauke@hauke-m.de>
Many x86 machines can boot from SD cards, and some embedded x86 devices
come with an eMMC. Include drivers for all common MMC/SDHCI controllers
to allow booting from SD/MMC on x86.
Signed-off-by: Daniel Golle <daniel@makrotopia.org>
Directly call the function "get_linux_version()" to get the integer
kernel version number.
Signed-off-by: Shiji Yang <yangshiji66@outlook.com>
Link: https://github.com/openwrt/openwrt/pull/19172
Signed-off-by: Hauke Mehrtens <hauke@hauke-m.de>
Currently, if OEM recovery flashes OpenWrt to second ubi1,
OpenWrt cannot boot. With this commit, recovery image is built
with initramfs kernel, so that it can boot from either ubi or ubi1.
This adds an extra step to OpenWrt installation from OEM:
user needs to sysupgrade from initramfs to full system.
Signed-off-by: Mateusz Krzak <kszaquitto+github@gmail.com>
Link: https://github.com/openwrt/openwrt/pull/18878
Signed-off-by: Hauke Mehrtens <hauke@hauke-m.de>
8mA driving will cause overshoot issue on SPI NAND. Change it to 4mA.
- Reference:
003744197a
On Linux mainline (mt7986.dtsi), spi's source clock is: clocks = <&topckgen CLK_TOP_MPLL_D2>, which is
208MHz. Usable clock division will be:
- 208/4=52MHz
- 208/6~=35MHz
- 208/8=26MHz
and so on
If we specify 50MHz for spi-max-frequency, it will actually run under about 35MHz. Most SPI NAND & NOR
flashes are capable of running with more than 52MHz, include Micorn MT29F4G01ABAFDWB on ZyXEL EX5601.
[Ref: #18752] To reach highest performance on mt7986, use spi-max-frequency = <520000000>. Basically,
this setting should work on all mt7986 PCBs since most mt7986 boards follow reference design. However,
other boards needs further test to guarantee stability.
Signed-off-by: Sky Huang <SkyLake.Huang@mediatek.com>
Tested-by: Aleksander Jan Bajkowski <olek2@wp.pl>
Link: https://github.com/openwrt/openwrt/pull/18813
Signed-off-by: Hauke Mehrtens <hauke@hauke-m.de>
In rtl931x_led_init, the number of leds per port is not properly set. It
currently uses a hardcoded value of 1 which seems to be taken initially
from a specific device. This hardcoded value assumes any port always has
exactly two leds.
The RTL930x variant - rtl930x_led_init - does a better job at this. So
take it and use it for RTL931x too with the corresponding register.
While at it, rename the function to a proper naming scheme.
Signed-off-by: Jonas Jelonek <jelonek.jonas@gmail.com>
Link: https://github.com/openwrt/openwrt/pull/19241
Signed-off-by: Hauke Mehrtens <hauke@hauke-m.de>
These cpu erratums are used by other SoCs, just remove them.
Signed-off-by: Chukun Pan <amadeus@jmu.edu.cn>
Link: https://github.com/openwrt/openwrt/pull/19380
Signed-off-by: Hauke Mehrtens <hauke@hauke-m.de>
These cpu erratums are used by other SoCs, just remove them.
Signed-off-by: Chukun Pan <amadeus@jmu.edu.cn>
Link: https://github.com/openwrt/openwrt/pull/19380
Signed-off-by: Hauke Mehrtens <hauke@hauke-m.de>
Move the following kernel symbol configs to generic:
COMPRESSED_INSTALL and IMX_SCMI related configs
Signed-off-by: Chukun Pan <amadeus@jmu.edu.cn>
Link: https://github.com/openwrt/openwrt/pull/19380
Signed-off-by: Hauke Mehrtens <hauke@hauke-m.de>
Dell/SonicWall APL27-0B1 (marketed as SonicPoint ACi) is a dual band
wireless access point. Very similar to already supported APL26-0AE,
which all antennas are external, while this variant has internal
antennas. End of life as of 2022-07-31.
Specification
SoC: QualcommAtheros QCA9550
RAM: 256 MB DDR2
Flash: 32 MB SPI NOR
WIFI: 2.4 GHz 3T3R integrated
5 GHz 3T3R QCA9890 oversized Mini PCIe card
Ethernet: 2x 10/100/1000 Mbps QCA8334
port labeled lan1 is PoE capable (802.3at)
USB: 1x 2.0
LEDs: LEDs: 6x which 5 are GPIO controlled and two of them are dual color
Buttons: 1x GPIO controlled
Serial: RJ-45 port, SonicWall pinout
baud: 115200, parity: none, flow control: none
Before flashing, be sure to have a copy of factory firmware, in case You
wish to revert to original firmware.
Installation
1. Prepare TFTP server with OpenWrt sysupgrade image and rename that
image to "ap135.bin".
2. Connect to one of LAN ports.
3. Connect to serial port.
4. Hold the reset button (small through hole on side of the unit),
power on the device and when prompted to stop autoboot, hit any key.
The held button can now be released.
5. Alter U-Boot environment with following commands:
setenv bootcmd bootm 0x9F110000
saveenv
6. Adjust "ipaddr" (access point, default is 192.168.1.1) and "serverip"
(TFTP server, default is 192.168.1.10) addresses in U-Boot
environment, then run following commands:
tftp 0x80060000 ap135.bin
erase 0x9F110000 +0x1EF0000
cp.b 0x80060000 0x9F110000 $filesize
7. After successful flashing, execute:
boot
8. The access point will boot to OpenWrt. Wait few minutes, until the
wrench LED will stop blinking, then it's ready for configuration.
Notes
By default no power is provided on USB port, so attached USB devices
won't enumerate. To change that enable regulator with:
echo "enabled" > /sys/devices/platform/output-usb-vbus/state
To disable power write "disabled" to the same file.
Ther regulator state will reset on reboot, consider running this command
on hotplug event or add it to /etc/rc.local. The hotplug event should
look like this:
if [ "${PRODUCT}" = "1d6b/2/606" ] && [ "${ACTION}" = "add" ]; then
echo "enabled" > /sys/devices/platform/output-usb-vbus/state
fi
Place it in /etc/hotplug.d/usb/10-usb-power.
Known issues
Initramfs image can't be bigger than specified kernel size, otherwise
bootloader will throw LZMA decompressing error. Switching to lzma-loader
should workaround that.
Signed-off-by: Tomasz Maciej Nowak <tmn505@gmail.com>
Link: https://patchwork.ozlabs.org/project/openwrt/patch/20250529202033.28250-2-tmn505@terefe.re/
Signed-off-by: Hauke Mehrtens <hauke@hauke-m.de>
Unfortunately they still apear with prolonged serial console usage.
While it's not common to use serial console past initial setup, alas
when the condition is hit the console is almost unusable.
Signed-off-by: Tomasz Maciej Nowak <tmn505@gmail.com>
Link: https://patchwork.ozlabs.org/project/openwrt/patch/20250618170045.473711-2-tmn505@terefe.re/
Signed-off-by: Hauke Mehrtens <hauke@hauke-m.de>
The bootup of the armsr target sometimes failed like this:
```
[ 0.762283] NET: Registered PF_INET6 protocol family
[ 0.791987] workqueue: Failed to create a worker thread: -EAGAIN
[ 0.801986] workqueue: Failed to create a rescuer kthread for wq "mld": -EAGAIN
[ 0.964017] NET: Unregistered PF_INET6 protocol family
```
Increase the maximum number of threads the kernel allows.
Link: https://github.com/openwrt/openwrt/pull/19376
Signed-off-by: Hauke Mehrtens <hauke@hauke-m.de>
The Wavlink Aerial HD3 (WL-WN570HA2) is an AC1200 dual-band outdoor
access point. It supports 802.3AT/AF PoE and is IP67 waterproof.
It is based on the MediaTek MT7628DAN SoC and MT7613BEN WiFi 5 chip.
This model uses the 100Mbit LAN and 2.4Ghz WiFi elements of the
MT7628 and the 5Ghz WiFi of the MT7613.
Specification:
- SoC: MediaTek MT7628DAN (1C/1T) @ 580MHz
- RAM: 64MB DDR2 (integrated in SoC)
- FLASH: 16MB SPI NOR (Fudan FM25Q128A)
- Ethernet: 1x 10/100Mbps
- WiFi: 2.4/5 GHz 2T2R
- 2.4GHz MediaTek MT7628DAN bgn
- 5GHz MediaTek MT7613BEN nac
- Antennas: 2x detachable, dual-band 7dBi with RP-SMA connectors.
- USB: none
- BTN: Reset
- LED: 6 total: power; WAN/LAN; WiFi; WiFi low; WiFi med; Wifi high
- UART: surface-mount on PCB. Pins are marked via silkscreen.
pin1 (square pad, towards Ethernet)=Vcc, pin2=RX,
pin3=TX, pin4=GND. Settings: 57600/8N1.
NOTE: The TX & RX silkscreens were reversed on my test unit.
Installation:
1) This device requires a HTTP recovery procedure to do an initial load
of OpenWRT. You will need:
a. A web browser (private window recommended)
b. Configure an Ethernet interface to 192.168.1.x/24; don't use .1
c. Connect a cable between the computer and the Wavlink's PoE injector.
2) Put the Wavlink in HTTP recovery mode.
a. Do this by pressing and holding the reset button on the bottom while
powering the unit on.
b. As soon as all 6 LEDs light up blue (roughly 2-3 seconds), release
the button.
c. The LEDs should all remain lit, indicating it's in HTTP recovery.
3) Point the browser at http://192.168.1.1/index.html
4) Click "Choose File" and select the OpenWRT sysupgrade image.
5) Click the "Update Firmware" button and wait while the unit flashes
the image and reboots.
6) When the system comes back up fully, only the power LED will be lit.
Wait an extra minute then you should be able to reach OpenWRT on
http://192.168.1.1
5) Log into LuCI as root; there is no password.
Revert to the OEM Firmware:
--------------------------
* U-boot HTTP:
Follow the HTTP recovery steps, and use a firmware image downloaded
from Wavlink.
Signed-off-by: Jonathan Sturges <jsturges@redhat.com>
Link: https://github.com/openwrt/openwrt/pull/18856
Signed-off-by: Hauke Mehrtens <hauke@hauke-m.de>
Add/enable 2nd USB bus (integrated ath3k bluetooth) to dts. This already
exists in the qca956x dtsi, adding the pointer here to bring the bluetooth to life.
The 2nd bus hosts the integrated bluetooth at 0x1b400000.
See in the comments for more info:
c5b7ec8cee
Tested-by: Russ Innes <russ.innes@gmail.com> on Ubiquiti Amplifi HD .
Signed-off-by: Russ Innes <russ.innes@gmail.com>
Link: https://github.com/openwrt/openwrt/pull/19303
Signed-off-by: Hauke Mehrtens <hauke@hauke-m.de>
This device is similar to the TP-Link EX220 v1.
The differences are the number of ports (3 LANs
and 1 WAN) and the number of LEDs (1 LED RGB)
Hardware
--------
CPU: MediaTek MT7621 DAT
RAM: 128MB DDR3 (integrated)
FLASH: 16MB SPI-NOR
WiFi: MediaTek MT7905 + MT7975 (2.4 / 5 DBDC) 802.11ax
SERIAL: 115200 8N1
LED - (TX - RX - GND - 3V3 ) - ETH ports
Installation
------------
Flashing is only possible via a serial connection using the sysupgrade
image; the factory image must be signed. You can flash the sysupgrade
image directly through the U-Boot console, or preferably, by booting the
initramfs image and flashing with the sysupgrade command. Follow these
steps for sysupgrade flashing:
1. Establish a UART serial connection.
2. Set up a TFTP server at 192.168.0.2 and copy the initramfs image
there.
3. Power on the device and press any key to interrupt normal boot.
4. Load the initramfs image using tftpboot.
5. Boot with bootm.
6. If you haven't done so already, back up all stock mtd partitions.
7. Copy the sysupgrade image to the router.
8. Flash OpenWrt through either LuCI or the sysupgrade command. Remember
not to attempt saving settings.
Revert to stock firmware
------------------------
Flash stock firmware via OEM web-recovery mode. If you don't have access
to the stock firmware image, you will need to restore the firmware
partition backed up earlier.
Web-Recovery
------------
The router supports an HTTP recovery mode:
1. Turn off the router.
2. Press the reset button and power on the device.
3. When the LED start flashing, release reset and quickly press it
again.
The interface is reachable at 192.168.0.1 and supports installation of
the OEM factory image. Note that flashing OpenWrt this way is not
possible, as mentioned above.
Signed-off-by: Gustavo Curi <gpcuri@land.ufrj.br>
Link: https://github.com/openwrt/openwrt/pull/19104
Signed-off-by: Hauke Mehrtens <hauke@hauke-m.de>
Since not every device sets an ubifs partition name as the same as their
parent mtd partition, this change allows mount_ubi_part to usable in
other devices
Signed-off-by: Yonghyu Ban <yhban@silicon.moe>
Link: https://github.com/openwrt/openwrt/pull/19203
Signed-off-by: Hauke Mehrtens <hauke@hauke-m.de>
**Huasifei WH3000 Pro**
Portable Wi-Fi 6 travel router based on MediaTek MT7981A SoC. MT7981B+MT7976CN+RTL8221B Dual Core 1.3GHZ with 5G modems module and PWM Fan.
**Specifications**
SoC: Filogic 820 MT7981A (1.3GHz)
RAM: DDR4 1GB
Flash: eMMC 8GB
WiFi: 2.4GHz and 5GHz with 3 antennas
Ethernet:
1x WAN (10/100/1000M)
1x LAN (10/100/1000/2500M)
USB: 1x USB 3.0 port
Two buttons: power/reset and mode (BTN_0)
LEDS: blue, red, blue+red=pink
UART: 3.3V, TX, RX, GND / 115200 8N1
**Installation via U-Boot rescue**
1. Set static IP 192.168.1.2 on your computer and default route as 192.168.1.1
2. Connect to the WAN port and hold the reset button while booting the device.
3. Wait for the LED to blink 5 times, and release the reset button.
4. Open U-boot web page on your browser at http://192.168.1.1
5. Select the OpenWRT sysupgrade image, upload it, and start the upgrade.
6. Wait for the router to flash the new firmware.
7. Wait for the router to reboot itself.
**Installation via sysupgrade**
Just flash sysupgrade file via [LuCI upgrade page](http://192.168.1.1/cgi-bin/luci/admin/system/flash) without saving the settings.
**Installation via SSH**
Upload the file to the router `/tmp` directory, `ssh root@192.168.1.1` and issue a command:
```
sysupgrade -n /tmp/openwrt-mediatek-filogic-huasifei_wh3000-pro-squashfs-sysupgrade.bin
```
**Factory MAC**
You can find your Factory MAC which is mentioned on the box at `/dev/mmcblck0p2` partition `factory` starting from `0x4`
```
dd if=/dev/mmcblk0p2 bs=1 skip=4 count=6 | hexdump -C
```
Cherry-picked from 949d0bd77a
Fixed `green` to `blue` LED in dts, added `SUPPORTED_DEVICES += huasifei,fudy-pro` - to make sysupgrade compatible with factory QWRT/Lede fork firmware.
Signed-off-by: Fil Dunsky <filipp.dunsky@gmail.com>
Link: https://github.com/openwrt/openwrt/pull/19315
Signed-off-by: Hauke Mehrtens <hauke@hauke-m.de>
The operating mode of a SerDes must be aligned with the attached PHY or
SFP module. That does not only require to change the protocol (e.g. SGMII,
10Gbase-R, ...) but also the speed (e.g. 1.25G). For this the SerDes must
be re-initialized properly.
- It must be taken into power down
- The PLL speed must be set
- Maybe the CMU (clock management unit) must be resetted
- The new mode must be set
- The state machine must be resetted
- The power must be reactivated
Until now this sequence is bugged. First the driver relies on a clean
setup from U-Boot (rtk network on) and second trying to to change mode
and PLL speeds does not work at all. And not to forget: Currently two
adjacent SerDes cannot drive SGMII/HSGMII at the same time. Fix this by
taking care about the right SerDes/PLL/CMU command init order.
P.S. This code is inspired by the work of Jan Hofmann, who tried to
enable parallel SGMII/HSGMII mode. The only missing bit was a proper CMU
reset sequence.
Signed-off-by: Jan Hoffmann <jan@3e8.eu>
Signed-off-by: Markus Stockhausen <markus.stockhausen@gmx.de>
Link: https://github.com/openwrt/openwrt/pull/19220
Signed-off-by: Robert Marko <robimarko@gmail.com>
Changing the node names arbitrarily broke existing configurations, which
rely on the device path in /etc/config/wireless.
Revert that part of the change without altering the compatible strings.
Fixes: 7e09959efd ("mac80211: fix wmac node names")
Signed-off-by: Felix Fietkau <nbd@nbd.name>
