The nRESET pins of the RTL8224 PHY on the MCX3 are wired to GPIO6 of the
SoC, but this was never described in the devicetree.
Commit c99a30668d ("realtek: add RTL8224 initialization to Realtek
driver") introduced support for reinitializing RTL8224 PHYs, and commit
084da38a2e ("realtek: mdio: activate multiple busses") allowed the MDIO
bus provider load the devicetree properties to the bus, including reset
descriptors. With both in place, a bus level PHY reset via the hardware pin
is now correctly triggered before reinitialization.
Add the missing reset-gpios property so the PHY can be reset via the
hardware pin.
Signed-off-by: Sven Eckelmann <sven@narfation.org>
Link: https://github.com/openwrt/openwrt/pull/22966
Signed-off-by: Robert Marko <robimarko@gmail.com>
Use regmap_assign_bits() where it improves readability. With this
there is no need to calculate masks and values in separate lines.
Splitting the single update_bits() in rtmdio_931x_setup_polling()
into two separate assign_bits() is uncritical.
Signed-off-by: Markus Stockhausen <markus.stockhausen@gmx.de>
Link: https://github.com/openwrt/openwrt/pull/23099
Signed-off-by: Hauke Mehrtens <hauke@hauke-m.de>
Add the registers, family id and cpu port defines to the mach header.
Since RTL96xx SoCs has additional "subtype" info, add the respective
property to soc_info struct to be used in prom file.
The same way as rtl838x, the chip_info register requires 0xa to be
written. Similarly, 0xb must be written to get the subtype info.
There doesn't seem any check for testchip in RTL96xx so, we ignore it.
Add subtype information to set_system_type function if it is present
using the added subtype variable.
There are some RTL9607 chips out there with 512MB so add the check
for RTL9607 in the prepare_highmem. The registers are the same as
in RTL9300 so nothing else need to be changed.
Signed-off-by: Rustam Adilov <adilov@tutamail.com>
Link: https://github.com/openwrt/openwrt/pull/23023
Signed-off-by: Hauke Mehrtens <hauke@hauke-m.de>
Refresh the patch to account for recent changes in the generic kernel
patches. Makes the CI kernel patch check happy again.
Fixes: c271123724 ("generic: 6.18: fix MediaTek USXGMII driver")
Signed-off-by: Jonas Jelonek <jelonek.jonas@gmail.com>
Link: https://github.com/openwrt/openwrt/pull/23127
Signed-off-by: Robert Marko <robimarko@gmail.com>
The USXGMII_10GDXGMII and USXGMII_10GQXGMII early-return was added
when the submode register was not yet programmed, making those modes
effectively unconfigurable. With the submode now wired up at probe
time and written from the set_mode path, the gating is no longer
needed.
Keep the XSGMII gate - RTL8218D/E bring-up through the proprietary
10G SGMII path is still unimplemented - and rewrite the surrounding
comment accordingly.
Signed-off-by: Jonas Jelonek <jelonek.jonas@gmail.com>
Link: https://github.com/openwrt/openwrt/pull/23120
Signed-off-by: Robert Marko <robimarko@gmail.com>
Complete the USXGMII submode table with the four values that were
missing so far:
0x01 10GDX (2 x 5G)
0x03 5GSX (1 x 5G)
0x04 5GDX (2 x 2.5G)
0x05 2_5GSX (1 x 2.5G)
Together with the existing 10GSX (0x00) and 10GQX (0x02) this covers
all six USXGMII modes the driver declares. Add a corresponding mapping
to the hw_mode table too to cover them properly there.
Replace the switch in rtpcs_93xx_sds_apply_usxgmii_submode() with a
sparse lookup table indexed by hw_mode, using -1 as the sentinel for
modes without a submode value. Non-USXGMII modes silently no-op as
before; a USXGMII mode hitting a SerDes without an allocated submode
register now returns -EOPNOTSUPP, catching configuration mismatches
that would previously have been silently dropped.
Signed-off-by: Jonas Jelonek <jelonek.jonas@gmail.com>
Link: https://github.com/openwrt/openwrt/pull/23120
Signed-off-by: Robert Marko <robimarko@gmail.com>
USXGMII submode (10GSX vs 10GQX) is selected through a dedicated
register at 0x13e8, independent of the MAC and IP mode registers.
Without programming it, USXGMII-QX ports initialise as single-lane
SX and fail to link up correctly; MAC and IP mode alone are
insufficient for a working USXGMII setup.
The register packs 12 x 5-bit entries for SerDes 2..13, six per
32-bit word, non-straddling (bits 0..29 used, 30..31 padded). This
matches the available register dumps and the SDK's
reg_array_field_write() non-CROSS_REGISTERS path, which derives the
bit position as ((index - larray) % (32 / width)) * width and
accesses only a single 32-bit word. The submode values are identical
to RTL930x, so the shared RTPCS_93XX_SDS_USXGMII_SUBMODE_* defines
are reused.
Allocate the regmap_field at probe time with coordinates computed
from the SerDes ID; the regular packing needs no lookup table. Call
rtpcs_93xx_sds_apply_usxgmii_submode() from the set_mode dispatcher
after set_ip_mode - the helper's null-guard and mode filter leave
non-USXGMII paths unchanged.
Signed-off-by: Jonas Jelonek <jelonek.jonas@gmail.com>
Link: https://github.com/openwrt/openwrt/pull/23120
Signed-off-by: Robert Marko <robimarko@gmail.com>
PHY drivers might need access to NVMEM or the filesystem to load
calibration/initialization data. The driver will then return -EPROBE_DEFER
to signal to the device core that the probe should be retried multiple
times again in the 10s driver_deferred_probe_timeout.
But when the switch driver calls dsa_register_switch(), it needs to connect
the PHYs directly. As result, all PHYs without an driver will automatically
get the default driver (either `genphy_c45_driver` or `genphy_driver`)
assigned and initialized. But for PHYs with the additional initialization
data from NVMEM/fs, this will usually result in not working PHYs.
Since there are Realtek based boards with RTL826x PHYs and the new driver
loads the initialization/patch values from rootfs, it is necessary to check
in the beginning of the probe function whether the PHYs are ready and the
probing can continue.
If some driver is still without driver after the deferred probe period
ended, the loading will just continue and the generic PHY drivers will
still be used.
Closes: #22811
Co-authored-by: Jonas Jelonek <jelonek.jonas@gmail.com>
Co-authored-by: Markus Stockhausen <markus.stockhausen@gmx.de>
Signed-off-by: Sven Eckelmann <sven@narfation.org>
Link: https://github.com/openwrt/openwrt/pull/23075
Signed-off-by: Robert Marko <robimarko@gmail.com>
RTL930x and RTL931x share a set of extras around MAC mode writes:
- a post-write delay (kept for consistency with the original RTL930x
behaviour; harmless on RTL931x)
- the force-mode bit (RTL931x only, nullable field)
Add rtpcs_93xx_sds_set_mac_mode() as a shared wrapper around the
generic rtpcs_sds_set_mac_mode() that applies each of these extras
unconditionally; the nullable field makes the force-bit write a no-op
on RTL930x.
Route the three RTL93xx call sites (the 930x and 931x set_mode
dispatchers, and 931x set_ip_mode's OFF transition) through the
wrapper, removing the duplicated force-bit handling from each.
The USXGMII submode write stays out of the wrapper and is called
explicitly from the 930x dispatcher via rtpcs_93xx_sds_apply_usxgmii_submode().
Keeping submode as a separate step leaves room for RTL931x to apply it
from its IP-mode path once the submode register is wired up, without
retrofitting a MAC-mode wrapper with side effects.
Signed-off-by: Jonas Jelonek <jelonek.jonas@gmail.com>
Link: https://github.com/openwrt/openwrt/pull/23040
Signed-off-by: Robert Marko <robimarko@gmail.com>
RTL931x uses a regular 8-bit-per-SerDes layout in SERDES_MODE_CTRL, so
the reg_field can be computed in the probe hook with simple arithmetic.
The 8-bit-per-SerDes field is split into a 7-bit mac_mode (bits 0..6)
and a 1-bit mac_mode_force (bit 7), each written independently via its
own regmap_field. The mac_mode is widened to 7 bits (rather than the
5 bits strictly needed for the mode value) so MAC mode writes also
clear bit 5 (FEC enable) and bit 6 (10G speedup), matching the original
behaviour where the full 8-bit mask cleared these bits on every mode
change. FEC and speedup are mode-dependent and not yet programmed by
the driver; keeping them cleared leaves headroom for future support
without changing the effective register value.
rtpcs_931x_sds_reset() is updated to save and restore both fields
across the off/on cycle, preserving the original force-bit handling.
rtpcs_931x_sds_set_mode() uses the generic rtpcs_sds_set_mac_mode() and
sets the force bit explicitly; the same sequence also appears in
rtpcs_931x_sds_set_ip_mode()'s OFF transition. Both are folded into
the shared RTL93xx wrapper in a later commit.
Signed-off-by: Jonas Jelonek <jelonek.jonas@gmail.com>
Link: https://github.com/openwrt/openwrt/pull/23040
Signed-off-by: Robert Marko <robimarko@gmail.com>
RTL930x packs 5-bit mode fields across four registers at irregular
positions. Express this as a static reg_field table indexed by SerDes
ID; the probe hook allocates the corresponding regmap_field. The
USXGMII submode register follows the same pattern with its own
reg_field table, allocated only for 10G-capable SerDes (id 2..9).
The generic rtpcs_sds_set_mac_mode() replaces the old
__rtpcs_930x_sds_set_mac_mode() helper. The previous behaviour of
writing OFF before the target mode is intentionally dropped — it was
RTL930x-specific and not required by the hardware.
The variant-level rtpcs_930x_sds_set_mode() is kept as a pure dispatch
between the IP mode path (set_ip_mode) and the MAC mode path. The
USXGMII submode write is factored into rtpcs_93xx_sds_apply_usxgmii_submode(),
which derives the submode value from hw_mode and no-ops on SerDes
without the submode register.
The __rtpcs_930x_sds_get_mac_mode() and __rtpcs_930x_sds_get_usxgmii_submode()
helpers are dropped. They were __always_unused and depended on the
removed parallel arrays. A future get_mode path will be added if a
caller needs it, likely mirroring the setter's wrapper shape.
Signed-off-by: Jonas Jelonek <jelonek.jonas@gmail.com>
Link: https://github.com/openwrt/openwrt/pull/23040
Signed-off-by: Robert Marko <robimarko@gmail.com>
RTL839x packs the SerDes MAC mode in MAC_SERDES_IF_CTRL with a regular
per-SerDes layout, so the regmap_field can be computed directly in the
probe hook rather than declared as a static table.
Mode values (currently only OFF and QSGMII) move into a static
rtpcs_839x_sds_hw_mode_vals[] table. Values for 100BASEX, 1000BASEX
and SGMII from the vendor SDK are kept as comments for future
reference — they are not yet exercised here.
With no variant-specific extras (no force bit, no companion register,
no submode), rtpcs_839x_sds_set_mode() is removed; setup_serdes calls
the generic rtpcs_sds_set_mac_mode() directly.
Signed-off-by: Jonas Jelonek <jelonek.jonas@gmail.com>
Link: https://github.com/openwrt/openwrt/pull/23040
Signed-off-by: Robert Marko <robimarko@gmail.com>
Replace rtpcs_838x_sds_set_mode()'s inline shift/mask arithmetic with
a regmap_field computed and allocated at probe time. The field layout
is regular (5-bit per SerDes, reverse-packed in SDS_MODE_SEL), so the
position can be derived arithmetically from the SerDes ID rather than
declared in a table.
The function keeps its wrapper role because SerDes 4 and 5 have a
second companion register (INT_MODE_CTRL) with its own per-mode value
encoding. Since RTL838x is the only variant with this quirk and the
register is written from only one call site, it is kept inline rather
than abstracted into its own config table.
Signed-off-by: Jonas Jelonek <jelonek.jonas@gmail.com>
Link: https://github.com/openwrt/openwrt/pull/23040
Signed-off-by: Robert Marko <robimarko@gmail.com>
All four Realtek PCS variants (RTL838x, RTL839x, RTL930x, RTL931x)
configure the SerDes MAC mode by writing a register field whose layout
varies per variant — different base registers, different bit positions,
and in some cases per-SerDes packing that isn't arithmetically regular.
Add the common infrastructure to express this uniformly:
- per-SerDes regmap_field pointers in a new 'swcore_regs' anonymous
struct on rtpcs_serdes: mac_mode, mac_mode_force (931x only, nullable)
and usxgmii_submode (930x only, nullable).
- a per-variant mode-value table pointer (sds_hw_mode_vals) on
rtpcs_config, keyed by enum rtpcs_sds_mode. Values are s16 with -1 as
the "unsupported" sentinel — u8 with 0 would collide with RTL839x's
OFF value (0x0).
- a generic rtpcs_sds_set_mac_mode() that looks up the value for the
requested mode and writes it via the regmap_field.
Variant-specific extras (post-write delay, force bit, companion register
writes, USXGMII submode handling) will be added in per-variant wrappers
in the following commits.
Signed-off-by: Jonas Jelonek <jelonek.jonas@gmail.com>
Link: https://github.com/openwrt/openwrt/pull/23040
Signed-off-by: Robert Marko <robimarko@gmail.com>
Remove the last sw() macros from the ethernet driver.
With this drop the required include line.
Signed-off-by: Markus Stockhausen <markus.stockhausen@gmx.de>
Link: https://github.com/openwrt/openwrt/pull/23067
Signed-off-by: Hauke Mehrtens <hauke@hauke-m.de>
Use regmap_assign_bits() for conversion and much simpler code.
Signed-off-by: Markus Stockhausen <markus.stockhausen@gmx.de>
Link: https://github.com/openwrt/openwrt/pull/23067
Signed-off-by: Hauke Mehrtens <hauke@hauke-m.de>
Besides converting some functions to regmap do some minor
refactoring for rteth_931x_init_mac().
- Use dev_err() instead of classic print functions
- Harmonize ALE_INIT error handling. ALE_INIT_2 has the same
logic as the other registers. The reset is finished as soon
as the register is completely zero.
- From testing 100ms poll timeout seems to be sufficient
Signed-off-by: Markus Stockhausen <markus.stockhausen@gmx.de>
Link: https://github.com/openwrt/openwrt/pull/23067
Signed-off-by: Hauke Mehrtens <hauke@hauke-m.de>
Make use of regmap in rteth_mac_link_down and rteth_mac_link_up.
Signed-off-by: Markus Stockhausen <markus.stockhausen@gmx.de>
Link: https://github.com/openwrt/openwrt/pull/23067
Signed-off-by: Hauke Mehrtens <hauke@hauke-m.de>
Use regmap in the following functions
- rteth_838x_hw_stop()
- rteth_839x_hw_stop()
- rteth_930x_hw_stop()
- rteth_931x_hw_stop()
Signed-off-by: Markus Stockhausen <markus.stockhausen@gmx.de>
Link: https://github.com/openwrt/openwrt/pull/23067
Signed-off-by: Hauke Mehrtens <hauke@hauke-m.de>
The Rollball command byte needs to be written last. Otherwise the
controller might access the wrong register or write the wrong value.
Fixes: 1fc19bc06e ("realtek: rtl93xx: mdio-smbus support for clause 45 and Rollball SFPs")
Signed-off-by: Jan Hoffmann <jan@3e8.eu>
Link: https://github.com/openwrt/openwrt/pull/23049
Signed-off-by: Hauke Mehrtens <hauke@hauke-m.de>
At least the XikeStor SKT-2.5G-100M SFP module seems to internally use
MDIO address 0 to access the PHY. This module allows accessing PHY
registers using Rollball protocol on address 0x51, and also provides
read-only C22 access on address 0x56. However, after disabling the
PHYAD0 configuration bit, only 0xffff can be read via both methods
(except for MMD device 30 which can still be accessed).
Since having MDIO address 0 enabled shouldn't do any harm on SFP modules
just leave the configuration bit alone in that case.
Signed-off-by: Jan Hoffmann <jan@3e8.eu>
Link: https://github.com/openwrt/openwrt/pull/23065
Signed-off-by: Hauke Mehrtens <hauke@hauke-m.de>
The defines should have been named SMI like everywhere else.
Signed-off-by: Markus Stockhausen <markus.stockhausen@gmx.de>
Link: https://github.com/openwrt/openwrt/pull/23070
Signed-off-by: Hauke Mehrtens <hauke@hauke-m.de>
This commit adds support for Hasivo S600WP-5GT-2SX-SE switch.
Device specification
--------------------
SoC Type: Realtek RTL9303
RAM: 128MB DDR3 SDRAM
Flash: Fudan FM25Q128A (16 MB)
Ethernet: 5x RTL8221B 10/100/1000/2500Mbps PHY (RJ45)
2x SFP+ 10G (I2C/DOM via bit-banged GPIO)
LEDs: 1x power green (no control)
1x system green (via RTL9303 GPIO)
3x RJ45 LEDs/port (HC595 shift regs on LED SPI)
1x Green (1G link)
1x Green (10M/100M link)
1x Orange (2.5G link)
2x SFP+ LEDs/port (HC595 shift regs on LED SPI)
1x 10G link
1x 1G link
Button: Reset
USB ports: None
Bootloader: Realtek U-Boot 2011.12
PoE: 1x HS104PTI for 802.3af/at/bt PoE (driver
will follow in a separate patch)
Installing OpenWrt
------------------
1. UART RJ45 requires soldering a connector to the empty footprint (RJ1).
(Amphenol RJHSEE380 or similar)
2. Connect to UART 38400@8n1, using Cisco Console Rollover cable (RS232)
3. Enter bootloader by pressing esc key during boot
4. Enter password `Hs2021cfgmg`
5. Type `XXXX` to get into U-Boot
6. Increase baudrate: `setenv baudrate 115200`
7. Use serial transfer (Y modem) via minicom:
`loady 0x84f00000`
Then send the initramfs image via minicom's Y modem upload.
8. `bootm 0x84f00000`
Now you should be in OpenWrt, and can use sysupgrade to install.
Signed-off-by: Carlo Szelinsky <github@szelinsky.de>
Link: https://github.com/openwrt/openwrt/pull/22310
Signed-off-by: Robert Marko <robimarko@gmail.com>
With the recent backport of the common PHY properties infrastructure
(phy-common-props and the phy_get_manual_{rx,tx}_polarity() helpers) to
OpenWrt, the generic `{rx,tx}-polarity` device tree properties are now
usable for the Realtek PCS driver. Switch the driver and all affected
boards from the local vendor-specific `realtek,pnswap-{rx,tx}` booleans
to the common properties.
Add a `config_polarity` SerDes op (implemented by RTL930x and RTL931x;
RTL838x/RTL839x polarity support not yet added) and a generic wrapper
that resolves the requested polarity via phy_get_manual_{rx,tx}_polarity()
and dispatches to the op. Variants without the op silently accept the
default polarity but warn when a non-default polarity is requested,
since that cannot be honored.
Move the polarity programming out of the variant setup_serdes callbacks
into rtpcs_pcs_config, so it runs before setup_serdes. This matches the
ordering used by the vendor SDK, which configures polarity first.
Update all board DTS files that previously used `realtek,pnswap-{rx,tx}`
to the new `{rx,tx}-polarity = <PHY_POL_INVERT>` property, and select
PHY_COMMON_PROPS from Kconfig.
Each SerDes now retains its DT node for later polarity lookup. Use
for_each_child_of_node_scoped for the iterator, and register a
devm_add_action_or_reset for each stored reference so it is released on
unbind or probe failure.
Signed-off-by: Jonas Jelonek <jelonek.jonas@gmail.com>
Link: https://github.com/openwrt/openwrt/pull/23044
Signed-off-by: Robert Marko <robimarko@gmail.com>
The hardware usually takes care that
- a packet is no larger than the available buffer
- has at least a FCS checksum of 4 bytes
Nevertheless be cautious and improve the existing
packet check. Just in case ...
Signed-off-by: Markus Stockhausen <markus.stockhausen@gmx.de>
Link: https://github.com/openwrt/openwrt/pull/22884
Signed-off-by: Robert Marko <robimarko@gmail.com>
Some occurrences of regmap_update_bits can be simplified by
using other regmap commands. Use set_bits/clear_bits/assign_bits
for better readability.
Signed-off-by: Markus Stockhausen <markus.stockhausen@gmx.de>
Link: https://github.com/openwrt/openwrt/pull/23039
Signed-off-by: Robert Marko <robimarko@gmail.com>
All consumers of legacy table commands have been refactored and
use the rtl_table helpers. Drop unused code.
rtl839x_exec_tbl2_cmd() cannot be dropped as it is still used
in the qos code. Keep it for now.
Signed-off-by: Markus Stockhausen <markus.stockhausen@gmx.de>
Link: https://github.com/openwrt/openwrt/pull/23037
Signed-off-by: Robert Marko <robimarko@gmail.com>
rtldsa_931x_stp_get() and rtl931x_stp_set() use legacy table code.
Replace that with rtl_table_xxx() helpers.
Signed-off-by: Markus Stockhausen <markus.stockhausen@gmx.de>
Link: https://github.com/openwrt/openwrt/pull/23037
Signed-off-by: Robert Marko <robimarko@gmail.com>
rtldsa_930x_stp_get() and rtl930x_stp_set() use legacy table code.
Replace that with rtl_table_xxx() helpers.
Signed-off-by: Markus Stockhausen <markus.stockhausen@gmx.de>
Link: https://github.com/openwrt/openwrt/pull/23037
Signed-off-by: Robert Marko <robimarko@gmail.com>
rtldsa_839x_stp_get() and rtl839x_stp_set() use legacy table code.
Replace that with rtl_table_xxx() helpers.
Signed-off-by: Markus Stockhausen <markus.stockhausen@gmx.de>
Link: https://github.com/openwrt/openwrt/pull/23037
Signed-off-by: Robert Marko <robimarko@gmail.com>
rtldsa_838x_stp_get() and rtl838x_stp_set() use legacy table code.
Replace that with rtl_table_xxx() helpers.
Signed-off-by: Markus Stockhausen <markus.stockhausen@gmx.de>
Link: https://github.com/openwrt/openwrt/pull/23037
Signed-off-by: Robert Marko <robimarko@gmail.com>
Use regmap in the four target specific hw_init() functions.
Signed-off-by: Markus Stockhausen <markus.stockhausen@gmx.de>
Link: https://github.com/openwrt/openwrt/pull/23038
Signed-off-by: Robert Marko <robimarko@gmail.com>
Another cleanup of legacy sw() code.
Signed-off-by: Markus Stockhausen <markus.stockhausen@gmx.de>
Link: https://github.com/openwrt/openwrt/pull/23038
Signed-off-by: Robert Marko <robimarko@gmail.com>
Another two functions that are cleaned from the legacy sw() macros.
Signed-off-by: Markus Stockhausen <markus.stockhausen@gmx.de>
Link: https://github.com/openwrt/openwrt/pull/23038
Signed-off-by: Robert Marko <robimarko@gmail.com>
The EXTERNAL_SFP_PHY macro is very strange. It has attributes
sfp and media but is not linked to any SFP definition. There
is nothing that the kernel can evaluate better than the classic
PHY_C22 macro.
Remark! For the current D-Link DGS-1210 consumers this macro
should be converted to a PHY_C22_SFP in the future. As of now
there is no hardware to identify the proper gpios and define
and verify the corresponding SFP ports. Add a TODO comment
where needed.
Signed-off-by: Markus Stockhausen <markus.stockhausen@gmx.de>
Link: https://github.com/openwrt/openwrt/pull/23036
Signed-off-by: Robert Marko <robimarko@gmail.com>
Several EXTERNAL macros have been removed in the past. There is
no need to distinguish if a phy is built into the SoC or is
attached externally.
Do the same for EXTERNAL_SFP_PHY_FULL. This macro denotes a phy
that has a SFP port attached to it. This is usually RTL8214FC
based. To be consistent with other macros name it PHY_C22_SFP.
While we are here make use of the new port/phy notation.
So PHY_C22_SFP(p, n, s) gives
- p: the overall port number
- n: the phy address on the current bus
- s: the sfp identifier
Signed-off-by: Markus Stockhausen <markus.stockhausen@gmx.de>
Link: https://github.com/openwrt/openwrt/pull/23036
Signed-off-by: Robert Marko <robimarko@gmail.com>
Import pending series introducing support for standalone PCS drivers.
This has previously already been used by the airoha target, and is
also the base for the closer-to-upstream patches for MediaTek MT7988
10G SerDes support.
In order to not having to diverge from upstream also backport series
for standardized handling for PHY and PCS SerDes pair polarity.
Signed-off-by: Daniel Golle <daniel@makrotopia.org>
Refactor rteth_hw_ring_setup() and rteth_839x_hw_en_rxtx().
Signed-off-by: Markus Stockhausen <markus.stockhausen@gmx.de>
Link: https://github.com/openwrt/openwrt/pull/23006
Signed-off-by: Robert Marko <robimarko@gmail.com>
Refactor rteth_setup_cpu_rx_rings() and rteth_838x_hw_en_rxtx().
Signed-off-by: Markus Stockhausen <markus.stockhausen@gmx.de>
Link: https://github.com/openwrt/openwrt/pull/23006
Signed-off-by: Robert Marko <robimarko@gmail.com>
Add support for RTL9313-based Zyxel XS1930-12HP, a 12-port Multi-Gig
switch with 10x 100M/1G/2.5G/5G/10G RJ45 and 2x 1G/10G SFP+ ports.
Hardware
========
- RTL9313 SoC
- 256MiB DDR3 RAM (Winbond W632GU6MB)
- 32MiB SPI-NOR Flash (Macronix MX25L25645G)
- 8x 100M/1G/2.5G/5G/10G RJ45 (Aquantia AQR813)
- 2x 100M/1G/2.5G/5G/10G RJ45 (2x Aquantia AQR113C)
- 2x 1G/10G SFP+
- PoE:
- Ports 1-8 with PoE++/802.3bt
- 2x RTL8239 + GigaDevice FD32F103 MCU
- RTL8231 for port LEDs
- LM96000 I2C hardware monitor
- 3-pin fans
- Front LEDs: PWR, SYS, CLOUD, LOCATOR, POE USAGE
- Console: TTL 3.3V, 115200 8N1
- Software chain:
- Bootbase/stripped-down U-Boot
- BootExt
- RAS/ZyNOS
Console
=======
The console port is a 4-pin header reachable without opening case.
Looking at the front port-side of the device, turn the device 90 degrees
clockwise. On this side, there's a rectangular opening in the honeycomb
structure. Pinout is (from left/front to right/back): GND RX TX VCC
Hardware quirks
===============
* The SFP signals RX_LOS, MOD_ABS and TX_FAULT do not have dedicated GPIO
lines each. Instead, there's a multiplexer (using GPIO12 and GPIO14)
which - depending on its state - connect this single GPIO line to RX_LOS,
MOD_ABS or TX_FAULT (GPIO19 for SFP1, GPIO27 for SFP2). This requires
a special adapter driver (which is backed by a gpio-mux) that makes
this hardware design and Linux' SFP core work together.
* SFP slots are disabled by default. GPIO6 and GPIO7 seems to be gates
for SFP1 and SFP2 respectively. The need to be pulled low to make SFP
modules work (i.e. respond to I2C requests and pass GPIO signals).
* Fan can only be set to SLOW or FAST mode, no real speed/PWM control.
Disclaimer
==========
PoE not yet supported.
Flashing OpenWrt will overwrite BootExtension + ZyNOS. BootExtension
functionality (e.g. initramfs boot as mentioned below) is not available
anymore then. The U-boot/Bootbase still has some limited functionality
which can be used in emergency cases.
Installation
============
Simple web upgrade:
1. Take the OpenWrt factory.bin image generated by the build.
2. In the ZyNOS web UI, login and go to Maintenance -> Firmware Upgrade.
3. Under "Boot Image", make sure the Config Boot Image is set to 1. In
other words, make sure the switch booted from firmware image 1 or it
will do so on next reboot.
This is crucial, otherwise OpenWrt cannot boot.
4. Below, select and upload the factory.bin image. After clicking
upgrade, the image will be flashed.
5. After flashing has finished, reboot the switch. It will now boot into
OpenWrt.
Initramfs boot
==============
NOTE: You need to use Xmodem transfer, the bootloader doesn't support
Ymodem nor any networking.
This only works as long as the default ZyNOS firmware is
installed.
1. Connect to the switch using serial and interrupt the boot process
to enter debug/recovery mode.
2. You need to unlock the bootloader. Use known methods [1] and [2] to
obtain the unlock code and unlock the bootloader with:
> ATEN 1,<unlock_code>
3. Upload the initramfs image using Xmodem:
> ATUP <address>,<file_length>
<address>: you may use any RAM address >= 0x80300000
<file_length>: length of image in bytes
4. After the transfer has finished, boot the image with:
> ATGO <address>
5. Wait for OpenWrt to boot. At this stage, it might be wise to create a
backup/dump of the Flash partitions.
Return to stock firmware
========================
1. Download the firmware for the switch from Zyxel website.
2. Unzip the download, there should be a .bin file with a alphanumeric
name.
3. Upload this file to running OpenWrt.
4. Run (use -F since the image doesn't have image metadata):
> sysupgrade -F <stock-firmware>.bin
5. Wait for the sysupgrade to succeed and the switch reboot. At the next
boot, ZyNOS should come up again.
Recovery
========
The Bootbase loader is actually a modified U-Boot variant. You can enter
it by spamming $ during the DRAM test.
The U-Boot shell can be unlocked with [1] and [2]. Note that the command
is slightly different, using a space instead of a comma, and lowercase:
> aten 1 <unlock_code>
You should now have more-or-less a standard RTK-U-boot shell from where
you can upload and write a new image to flash. Use e.g.:
> upgradeY image2 81000000 115200
Wait for the upgrade process to finish and reboot the switch.
===
[1] https://akao.co.uk/tools/zyxel_unlocker/
[2] https://www.ixo.de/info/zyxel_uclinux/
Signed-off-by: Jonas Jelonek <jelonek.jonas@gmail.com>
Link: https://github.com/openwrt/openwrt/pull/22909
Signed-off-by: Robert Marko <robimarko@gmail.com>
Add support for RTL9313-based Zyxel XS1930-12F, a 12-port Multi-Gig
switch with 8x 1G/10G SFP+ ports and 2x 100M/1G/2.5G/5G/10G RJ45.
Hardware
========
- RTL9313 SoC
- 256MiB DDR3 RAM (Nanya NT5CC128M16JR-EK)
- 32MiB SPI-NOR Flash (Macronix MX25L25645G)
- 10x 1G/10G SFP+
- 2x 100M/1G/2.5G/5G/10G RJ45 (2x Aquantia AQR113C)
- 2x RTL8231 for GPIO expansion + port LEDs
- TI PM555 GPIO expander
- LM96000 I2C hardware monitor
- 3-pin fan
- Front LEDs: PWR, SYS, CLOUD, LOCATOR
- Console: TTL 3.3V, 115200 8N1
- Software chain:
- Bootbase/stripped-down U-Boot
- BootExt
- RAS/ZyNOS
Console
=======
The console port is a 4-pin header reachable without opening case.
Looking at the front port-side of the device, turn the device 90 degrees
clockwise. On this side, there's a rectangular opening in the honeycomb
structure. Pinout is (from left/front to right/back): GND RX TX VCC
Hardware quirks
===============
* SFP slots are disabled by default. Several GPIO lines on the PM555
GPIO expander need to be pulled low to activate SFPs, one for each SFP
slot. Otherwise modules cannot respond to I2C requests and GPIO signals
do not reach the SoC.
* Fan can only be set to SLOW or FAST mode, no real speed/PWM control.
Disclaimer
==========
Flashing OpenWrt will overwrite BootExtension + ZyNOS. BootExtension
functionality (e.g. initramfs boot as mentioned below) is not available
anymore then. The U-boot/Bootbase still has some limited functionality
which can be used in emergency cases.
Installation
============
Simple web upgrade:
1. Take the OpenWrt factory.bin image generated by the build.
2. In the ZyNOS web UI, login and go to Maintenance -> Firmware Upgrade.
3. Under "Boot Image", make sure the Config Boot Image is set to 1. In
other words, make sure the switch booted from firmware image 1 or it
will do so on next reboot.
This is crucial, otherwise OpenWrt cannot boot.
4. Below, select and upload the factory.bin image. After clicking
upgrade, the image will be flashed.
5. After flashing has finished, reboot the switch. It will now boot into
OpenWrt.
Initramfs boot
==============
NOTE: You need to use Xmodem transfer, the bootloader doesn't support
Ymodem nor any networking.
This only works as long as the default ZyNOS firmware is
installed.
1. Connect to the switch using serial and interrupt the boot process
to enter debug/recovery mode.
2. You need to unlock the bootloader. Use known methods [1] and [2] to
obtain the unlock code and unlock the bootloader with:
> ATEN 1,<unlock_code>
3. Upload the initramfs image using Xmodem:
> ATUP <address>,<file_length>
<address>: you may use any RAM address >= 0x80300000
<file_length>: length of image in bytes
4. After the transfer has finished, boot the image with:
> ATGO <address>
5. Wait for OpenWrt to boot. At this stage, it might be wise to create a
backup/dump of the Flash partitions.
Return to stock firmware
========================
1. Download the firmware for the switch from Zyxel website.
2. Unzip the download, there should be a .bin file with a alphanumeric
name.
3. Upload this file to running OpenWrt.
4. Run (use -F since the image doesn't have image metadata):
> sysupgrade -F <stock-firmware>.bin
5. Wait for the sysupgrade to succeed and the switch reboot. At the next
boot, ZyNOS should come up again.
Recovery
========
The Bootbase loader is actually a modified U-Boot variant. You can enter
it by spamming $ during the DRAM test.
The U-Boot shell can be unlocked with [1] and [2]. Note that the command
is slightly different, using a space instead of a comma, and lowercase:
> aten 1 <unlock_code>
You should now have more-or-less a standard RTK-U-boot shell from where
you can upload and write a new image to flash. Use e.g.:
> upgradeY image2 81000000 115200
Wait for the upgrade process to finish and reboot the switch.
===
[1] https://akao.co.uk/tools/zyxel_unlocker/
[2] https://www.ixo.de/info/zyxel_uclinux/
Signed-off-by: Jonas Jelonek <jelonek.jonas@gmail.com>
Link: https://github.com/openwrt/openwrt/pull/22909
Signed-off-by: Robert Marko <robimarko@gmail.com>
Add support for RTL9313-based Zyxel XS1930-10, a 10-port Multi-Gig
switch with 8x 100M/1G/2.5G/5G/10G RJ45 and 2x 1G/10G SFP+ ports.
Hardware
========
- RTL9313 SoC
- 256MiB DDR3 RAM (Winbond W632GU6MB)
- 32MiB SPI-NOR Flash (Macronix MX25L25645G)
- 8x 100M/1G/2.5G/5G/10G RJ45 (Aquantia AQR813)
- 2x 1G/10G SFP+
- RTL8231 for port LEDs
- LM96000 I2C hardware monitor
- 3-pin fan
- Front LEDs: PWR, SYS, CLOUD, LOCATOR
- Console: TTL 3.3V, 115200 8N1
- Software chain:
- Bootbase/stripped-down U-Boot
- BootExt
- RAS/ZyNOS
Console
=======
The console port is a 4-pin header reachable without opening case.
Looking at the front port-side of the device, turn the device 90 degrees
clockwise. On this side, there's a rectangular opening in the honeycomb
structure. Pinout is (from left/front to right/back): GND RX TX VCC
Hardware quirks
===============
* The SFP signals RX_LOS, MOD_ABS and TX_FAULT do not have dedicated GPIO
lines each. Instead, there's a multiplexer (using GPIO12 and GPIO14)
which - depending on its state - connect this single GPIO line to RX_LOS,
MOD_ABS or TX_FAULT (GPIO19 for SFP1, GPIO27 for SFP2). This requires
a special adapter driver (which is backed by a gpio-mux) that makes
this hardware design and Linux' SFP core work together.
* SFP slots are disabled by default. GPIO6 and GPIO7 seems to be gates
for SFP1 and SFP2 respectively. The need to be pulled low to make SFP
modules work (i.e. respond to I2C requests and pass GPIO signals).
* Fan can only be set to SLOW or FAST mode, no real speed/PWM control.
Disclaimer
==========
Flashing OpenWrt will overwrite BootExtension + ZyNOS. BootExtension
functionality (e.g. initramfs boot as mentioned below) is not available
anymore then. The U-boot/Bootbase still has some limited functionality
which can be used in emergency cases.
Installation
============
Simple web upgrade:
1. Take the OpenWrt factory.bin image generated by the build.
2. In the ZyNOS web UI, login and go to Maintenance -> Firmware Upgrade.
3. Under "Boot Image", make sure the Config Boot Image is set to 1. In
other words, make sure the switch booted from firmware image 1 or it
will do so on next reboot.
This is crucial, otherwise OpenWrt cannot boot.
4. Below, select and upload the factory.bin image. After clicking
upgrade, the image will be flashed.
5. After flashing has finished, reboot the switch. It will now boot into
OpenWrt.
Initramfs boot
==============
NOTE: You need to use Xmodem transfer, the bootloader doesn't support
Ymodem nor any networking.
This only works as long as the default ZyNOS firmware is
installed.
1. Connect to the switch using serial and interrupt the boot process
to enter debug/recovery mode.
2. You need to unlock the bootloader. Use known methods [1] and [2] to
obtain the unlock code and unlock the bootloader with:
> ATEN 1,<unlock_code>
3. Upload the initramfs image using Xmodem:
> ATUP <address>,<file_length>
<address>: you may use any RAM address >= 0x80300000
<file_length>: length of image in bytes
4. After the transfer has finished, boot the image with:
> ATGO <address>
5. Wait for OpenWrt to boot. At this stage, it might be wise to create a
backup/dump of the Flash partitions.
Return to stock firmware
========================
1. Download the firmware for the switch from Zyxel website.
2. Unzip the download, there should be a .bin file with a alphanumeric
name.
3. Upload this file to running OpenWrt.
4. Run (use -F since the image doesn't have image metadata):
> sysupgrade -F <stock-firmware>.bin
5. Wait for the sysupgrade to succeed and the switch reboot. At the next
boot, ZyNOS should come up again.
Recovery
========
The Bootbase loader is actually a modified U-Boot variant. You can enter
it by spamming $ during the DRAM test.
The U-Boot shell can be unlocked with [1] and [2]. Note that the command
is slightly different, using a space instead of a comma, and lowercase:
> aten 1 <unlock_code>
You should now have more-or-less a standard RTK-U-boot shell from where
you can upload and write a new image to flash. Use e.g.:
> upgradeY image2 81000000 115200
Wait for the upgrade process to finish and reboot the switch.
===
[1] https://akao.co.uk/tools/zyxel_unlocker/
[2] https://www.ixo.de/info/zyxel_uclinux/
Signed-off-by: Jonas Jelonek <jelonek.jonas@gmail.com>
Link: https://github.com/openwrt/openwrt/pull/22909
Signed-off-by: Robert Marko <robimarko@gmail.com>
Add generic support for Zyxel's XS1930 10G switch lineup. This will be
used by subsequent patches to share common behavior/settings.
Common specs:
- Realtek RTL9313 switch SoC
- 256MB RAM
- 32MB Flash with shared layout
- different 10G copper/SFP port configurations
The devices use a proprietary software chain from Zyxel, consisting of:
- stripped-down, heavily modified U-boot masked as "Bootbase"
- BootExtension stage2 loader
- Thread-X based ZyNOS
Those devices require to add some symbols to the kernel config, i.e.
CONFIG_AQUANTIA_PHY for the used PHYs and symbols for GPIO peripherals
and muxes due to the hardware design.
Signed-off-by: Jonas Jelonek <jelonek.jonas@gmail.com>
Link: https://github.com/openwrt/openwrt/pull/22909
Signed-off-by: Robert Marko <robimarko@gmail.com>
Add a new recipe 'zyxel-zynos' which contains common
behavior/definitions for ZyNOS-based Zyxel devices which requirea
special image to be built using 'zynos-firmware' recipe.
Signed-off-by: Jonas Jelonek <jelonek.jonas@gmail.com>
Link: https://github.com/openwrt/openwrt/pull/22909
Signed-off-by: Robert Marko <robimarko@gmail.com>
Add a build recipe to build a ZyNOS firmware image using mkzynfw from
firmware-utils to produce an image that can be flashed with the web
interface of ZyNOS vendor firmware.
Signed-off-by: Jonas Jelonek <jelonek.jonas@gmail.com>
Link: https://github.com/openwrt/openwrt/pull/22909
Signed-off-by: Robert Marko <robimarko@gmail.com>
The whole driver often does some range checks of the SerDes ID to
restrict some functionality to a group of SerDes. However, having these
open-coded checks everywhere is rather confusing because it's not
obvious what it actually means.
Luckily, those checks give a good picture of what SerDes types we have:
- 5G: RTL838x, RTL839x (0-7, 10, 11), RTL930x (0, 1)
- 10G: RTL839x (8, 9, 12, 13), RTL930x (2-9), RTL931x (2-13)
- unknown: RTL930x (10, 11), RTL931x (0, 1)
Add a new enum and field in rtpcs_serdes for the type of a SerDes we
have. This is filled during SerDes probe, making use of the stub
implementations for that hook.. All SerDes ID range checks related to
this are replaced with corresponding checks of the SerDes type.
Signed-off-by: Jonas Jelonek <jelonek.jonas@gmail.com>
Link: https://github.com/openwrt/openwrt/pull/22941
Signed-off-by: Robert Marko <robimarko@gmail.com>
Add a per-SerDes probe hook to rtpcs_config, called once for each SerDes
during driver probe. This provides a place for variant-specific, one-time
per-SerDes initialization that doesn't fit into the existing controller-
level init hook — such as allocating per-lane regmap fields or assigning
per-SerDes metadata.
Add stub implementations for all variants for now. They will be used by
all variants in a subsequent comment. For RTL839x, reuse the existing
rtl839x_sds_init hook and move its call out of the global init.
Signed-off-by: Jonas Jelonek <jelonek.jonas@gmail.com>
Link: https://github.com/openwrt/openwrt/pull/22941
Signed-off-by: Robert Marko <robimarko@gmail.com>
Our USXGMII config only covers one single register of which kind there
are actually more. We only set a value for 'CFG_QHSG_TXCFG_MAC_CH0' but
there are additional registers for CH1-CH3. Those refer to the 4
USXGMII 'channels'. While the RTL930x part of the SDK doesn't set them
explicitly, from RTK setup SerDes dumps we can see they are usually
similarly set.
The RTL931x part of the SDK actually writes those register explicitly
during USXGMII. We just haven't implemented that so far. Thus, add this
to the USXGMII config for both RTL93xx.
Signed-off-by: Jonas Jelonek <jelonek.jonas@gmail.com>
Link: https://github.com/openwrt/openwrt/pull/22939
Signed-off-by: Robert Marko <robimarko@gmail.com>
