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realtek: rtl930x: psx8: specify RTL8224 reset GPIO

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The nRESET pins of the RTL8224 PHYs on the PSX8/PSX10 are wired to GPIO6
(lan1-4) + GPIO10 (lan5-8) of the SoC, but this was never described in the
devicetree.

GPIO 6 is the global reset shared by (logical) PHYs 0-3 on MDIO bus0. GPIO
10 is the global reset shared by (logical) PHYs 8-11 on mdio bus0. It is
intentionally not declared as reset-gpios on any bus: the MDIO driver /
phylink only support a single reset GPIO per bus, not two (or more). And a
GPIO can only be used as reset-gpio on a single PHY. Attaching it to a
single PHY would still reset the other PHYs on the same chip as a side
effect, leaving their software state out of sync with the hardware and
likely breaking them.

Signed-off-by: Sven Eckelmann <se@simonwunderlich.de>
Link: https://github.com/openwrt/openwrt/pull/23297
Signed-off-by: Robert Marko <robimarko@gmail.com>
This commit is contained in:
Sven Eckelmann 2026-04-17 08:50:26 +02:00 committed by Robert Marko
parent 80e53edc87
commit 12d41dce06
1 changed files with 34 additions and 0 deletions
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34
target/linux/realtek/dts/rtl9302_plasmacloud_common.dtsi
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@ -210,3 +210,37 @@
nvmem-cells = <&macaddr_ubootenv_ethaddr 8>;
nvmem-cell-names = "mac-address";
};
&gpio0 {
/*
* GPIO 6 is the global reset shared by (logical) PHYs 0-3 on MDIO bus0.
* It is intentionally not declared as reset-gpios on any bus: the MDIO
* driver / phylink only support a single reset GPIO per bus, not two
* (or more). And a GPIO can only be used as reset-gpio on a single PHY.
* Attaching it to a single PHY would still reset the other PHYs on
* the same chip as a side effect, leaving their software state out of
* sync with the hardware and likely breaking them.
*/
phy_reset1 {
gpio-hog;
gpios = <6 GPIO_ACTIVE_LOW>;
output-low;
line-name = "phy-reset-lan1-4";
};
/*
* GPIO 10 is the global reset shared by (logical) PHYs 8-11 on MDIO
* bus0. It is intentionally not declared as reset-gpios on any bus:
* the MDIO driver / phylink only support a single reset GPIO per bus,
* not two (or more). And a GPIO can only be used as reset-gpio on a
* single PHY. Attaching it to a single PHY would still reset the other
* PHYs on the same chip as a side effect, leaving their software state
* out of sync with the hardware and likely breaking them.
*/
phy_reset2 {
gpio-hog;
gpios = <10 GPIO_ACTIVE_LOW>;
output-low;
line-name = "phy-reset-lan5-8";
};
};