ixp4xx/kernel: drop v6.12 and default to v6.18
Drop the old kernel and move over to the latest. We hardly have any patches so this is a swift change. Link: https://github.com/openwrt/openwrt/pull/22933 Signed-off-by: Linus Walleij <linusw@kernel.org>
This commit is contained in:
Linus Walleij
parent
05b6a93173
commit
8f8276a5b7
@ -11,8 +11,7 @@ FEATURES:=dt squashfs gpio ext4 rootfs-part
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CPU_TYPE:=xscale
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SUBTARGETS:=generic
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KERNEL_PATCHVER:=6.12
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KERNEL_TESTING_PATCHVER:=6.18
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KERNEL_PATCHVER:=6.18
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define Target/Description
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Build firmware images for the IXP4xx XScale CPU
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@ -1,257 +0,0 @@
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CONFIG_ALIGNMENT_TRAP=y
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CONFIG_AMD_PHY=y
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CONFIG_ARCH_32BIT_OFF_T=y
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CONFIG_ARCH_HIBERNATION_POSSIBLE=y
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CONFIG_ARCH_IXP4XX=y
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CONFIG_ARCH_KEEP_MEMBLOCK=y
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CONFIG_ARCH_MIGHT_HAVE_PC_PARPORT=y
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CONFIG_ARCH_MULTIPLATFORM=y
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CONFIG_ARCH_MULTI_CPU_AUTO=y
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# CONFIG_ARCH_MULTI_V4 is not set
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# CONFIG_ARCH_MULTI_V4T is not set
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CONFIG_ARCH_MULTI_V4_V5=y
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CONFIG_ARCH_MULTI_V5=y
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CONFIG_ARCH_OPTIONAL_KERNEL_RWX=y
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CONFIG_ARCH_SELECT_MEMORY_MODEL=y
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CONFIG_ARCH_SPARSEMEM_ENABLE=y
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CONFIG_ARCH_STACKWALK=y
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CONFIG_ARCH_SUSPEND_POSSIBLE=y
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CONFIG_ARM=y
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CONFIG_ARM_APPENDED_DTB=y
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# CONFIG_ARM_ATAG_DTB_COMPAT is not set
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CONFIG_ARM_HAS_GROUP_RELOCS=y
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CONFIG_ARM_L1_CACHE_SHIFT=5
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CONFIG_ARM_PATCH_PHYS_VIRT=y
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CONFIG_ARM_THUMB=y
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CONFIG_ARM_UNWIND=y
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CONFIG_ATA=y
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CONFIG_ATAGS=y
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CONFIG_AUTO_ZRELADDR=y
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CONFIG_BINFMT_FLAT_ARGVP_ENVP_ON_STACK=y
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CONFIG_BLK_DEV_LOOP=y
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CONFIG_BLK_DEV_SD=y
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CONFIG_BLK_MQ_PCI=y
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CONFIG_BUFFER_HEAD=y
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CONFIG_CC_HAVE_STACKPROTECTOR_TLS=y
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CONFIG_CLKSRC_MMIO=y
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CONFIG_CLONE_BACKWARDS=y
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CONFIG_COMMON_CLK=y
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CONFIG_COMPACT_UNEVICTABLE_DEFAULT=1
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CONFIG_COMPAT_32BIT_TIME=y
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CONFIG_CPU_32v5=y
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CONFIG_CPU_ABRT_EV5T=y
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CONFIG_CPU_BIG_ENDIAN=y
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CONFIG_CPU_CACHE_VIVT=y
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CONFIG_CPU_CP15=y
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CONFIG_CPU_CP15_MMU=y
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CONFIG_CPU_ENDIAN_BE32=y
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CONFIG_CPU_MITIGATIONS=y
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CONFIG_CPU_PABRT_LEGACY=y
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CONFIG_CPU_THUMB_CAPABLE=y
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CONFIG_CPU_TLB_V4WBI=y
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CONFIG_CPU_USE_DOMAINS=y
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CONFIG_CPU_XSCALE=y
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CONFIG_CRC16=y
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CONFIG_CRYPTO_AUTHENC=m
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CONFIG_CRYPTO_CBC=m
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CONFIG_CRYPTO_CRC32C=y
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CONFIG_CRYPTO_DES=m
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CONFIG_CRYPTO_DEV_IXP4XX=m
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CONFIG_CRYPTO_ECB=m
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CONFIG_CRYPTO_HW=y
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CONFIG_CRYPTO_LIB_BLAKE2S_GENERIC=y
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CONFIG_CRYPTO_LIB_DES=m
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CONFIG_CRYPTO_LIB_GF128MUL=y
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CONFIG_CRYPTO_LIB_UTILS=y
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CONFIG_DEBUG_BUGVERBOSE=y
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CONFIG_DEBUG_INFO=y
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CONFIG_DEBUG_LL_INCLUDE="debug/8250.S"
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CONFIG_DEBUG_UART_8250=y
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CONFIG_DEBUG_UART_8250_SHIFT=2
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CONFIG_DEBUG_UART_PHYS=0xc8000003
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CONFIG_DEBUG_UART_VIRT=0xfec00003
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CONFIG_DMA_OPS=y
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CONFIG_DTC=y
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CONFIG_EDAC_ATOMIC_SCRUB=y
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CONFIG_EDAC_SUPPORT=y
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CONFIG_EXCLUSIVE_SYSTEM_RAM=y
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CONFIG_EXT4_FS=y
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# CONFIG_FARSYNC is not set
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CONFIG_FIXED_PHY=y
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CONFIG_FIX_EARLYCON_MEM=y
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CONFIG_FORCE_PCI=y
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# CONFIG_FRAMER is not set
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CONFIG_FS_IOMAP=y
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CONFIG_FS_MBCACHE=y
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CONFIG_FUNCTION_ALIGNMENT=0
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CONFIG_FWNODE_MDIO=y
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CONFIG_FW_LOADER_PAGED_BUF=y
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CONFIG_FW_LOADER_SYSFS=y
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CONFIG_GCC_ASM_GOTO_OUTPUT_WORKAROUND=y
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CONFIG_GENERIC_ALLOCATOR=y
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CONFIG_GENERIC_ATOMIC64=y
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CONFIG_GENERIC_BUG=y
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CONFIG_GENERIC_CLOCKEVENTS=y
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CONFIG_GENERIC_CPU_AUTOPROBE=y
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CONFIG_GENERIC_EARLY_IOREMAP=y
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CONFIG_GENERIC_IDLE_POLL_SETUP=y
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CONFIG_GENERIC_IRQ_MULTI_HANDLER=y
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CONFIG_GENERIC_IRQ_SHOW=y
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CONFIG_GENERIC_IRQ_SHOW_LEVEL=y
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CONFIG_GENERIC_LIB_DEVMEM_IS_ALLOWED=y
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CONFIG_GENERIC_PCI_IOMAP=y
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CONFIG_GENERIC_SCHED_CLOCK=y
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CONFIG_GENERIC_SMP_IDLE_THREAD=y
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CONFIG_GENERIC_STRNCPY_FROM_USER=y
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CONFIG_GENERIC_STRNLEN_USER=y
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CONFIG_GLOB=y
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CONFIG_GPIOLIB_IRQCHIP=y
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CONFIG_GPIO_CDEV=y
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CONFIG_GPIO_GENERIC=y
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CONFIG_GPIO_GW_PLD=y
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CONFIG_GPIO_IXP4XX=y
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CONFIG_GRO_CELLS=y
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CONFIG_HARDIRQS_SW_RESEND=y
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CONFIG_HAS_DMA=y
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CONFIG_HAS_IOMEM=y
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CONFIG_HAS_IOPORT=y
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CONFIG_HAS_IOPORT_MAP=y
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CONFIG_HDLC=y
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CONFIG_HWMON=y
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CONFIG_HW_RANDOM=y
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CONFIG_HW_RANDOM_IXP4XX=y
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CONFIG_HZ_FIXED=0
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CONFIG_HZ_PERIODIC=y
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CONFIG_I2C=y
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CONFIG_I2C_ALGOBIT=y
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CONFIG_I2C_BOARDINFO=y
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CONFIG_I2C_CHARDEV=y
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CONFIG_I2C_GPIO=y
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CONFIG_I2C_IOP3XX=y
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CONFIG_INITRAMFS_SOURCE=""
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CONFIG_INTEL_IXP4XX_EB=y
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CONFIG_IRQCHIP=y
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CONFIG_IRQSTACKS=y
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CONFIG_IRQ_DOMAIN=y
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CONFIG_IRQ_DOMAIN_HIERARCHY=y
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CONFIG_IRQ_FORCED_THREADING=y
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CONFIG_IRQ_WORK=y
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# CONFIG_IWMMXT is not set
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CONFIG_IXP4XX_ETH=y
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CONFIG_IXP4XX_HSS=y
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CONFIG_IXP4XX_IRQ=y
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CONFIG_IXP4XX_NPE=y
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CONFIG_IXP4XX_QMGR=y
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CONFIG_IXP4XX_TIMER=y
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CONFIG_IXP4XX_WATCHDOG=y
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CONFIG_JBD2=y
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CONFIG_LEDS_GPIO=y
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CONFIG_LEGACY_PTYS=y
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CONFIG_LEGACY_PTY_COUNT=256
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CONFIG_LIBFDT=y
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CONFIG_LOCK_DEBUGGING_SUPPORT=y
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CONFIG_MDIO_BUS=y
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CONFIG_MDIO_DEVICE=y
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CONFIG_MDIO_DEVRES=y
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CONFIG_MFD_SYSCON=y
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CONFIG_MIGRATION=y
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CONFIG_MMU_LAZY_TLB_REFCOUNT=y
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CONFIG_MODULES_USE_ELF_REL=y
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CONFIG_MTD_CFI_ADV_OPTIONS=y
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# CONFIG_MTD_CFI_GEOMETRY is not set
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CONFIG_MTD_OTP=y
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CONFIG_MTD_PHYSMAP=y
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CONFIG_MTD_PHYSMAP_IXP4XX=y
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CONFIG_MTD_REDBOOT_PARTS=y
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CONFIG_MTD_SPLIT_FIRMWARE=y
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CONFIG_MTD_SPLIT_FIRMWARE_NAME="linux"
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CONFIG_NEED_DMA_MAP_STATE=y
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CONFIG_NEED_KUSER_HELPERS=y
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CONFIG_NEED_PER_CPU_KM=y
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CONFIG_NET_DEVLINK=y
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CONFIG_NET_EGRESS=y
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CONFIG_NET_INGRESS=y
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CONFIG_NET_PTP_CLASSIFY=y
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CONFIG_NET_SELFTESTS=y
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CONFIG_NET_VENDOR_XSCALE=y
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CONFIG_NET_XGRESS=y
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CONFIG_NLS=y
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CONFIG_NVMEM=y
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CONFIG_NVMEM_LAYOUTS=y
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CONFIG_NVMEM_SYSFS=y
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CONFIG_OF=y
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CONFIG_OF_ADDRESS=y
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CONFIG_OF_EARLY_FLATTREE=y
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CONFIG_OF_FLATTREE=y
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CONFIG_OF_GPIO=y
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CONFIG_OF_IRQ=y
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CONFIG_OF_KOBJ=y
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CONFIG_OF_MDIO=y
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CONFIG_OLD_SIGACTION=y
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CONFIG_OLD_SIGSUSPEND3=y
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CONFIG_PAGE_OFFSET=0xC0000000
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CONFIG_PAGE_POOL=y
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CONFIG_PAGE_SIZE_LESS_THAN_256KB=y
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CONFIG_PAGE_SIZE_LESS_THAN_64KB=y
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CONFIG_PAHOLE_HAS_LANG_EXCLUDE=y
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CONFIG_PATA_IXP4XX_CF=y
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CONFIG_PCI=y
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CONFIG_PCI_DOMAINS=y
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CONFIG_PCI_DOMAINS_GENERIC=y
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CONFIG_PCI_IXP4XX=y
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CONFIG_PERF_USE_VMALLOC=y
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CONFIG_PGTABLE_LEVELS=2
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CONFIG_PHYLIB=y
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CONFIG_PHYLIB_LEDS=y
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CONFIG_PHYLINK=y
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CONFIG_POWER_RESET=y
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CONFIG_POWER_RESET_GPIO=y
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CONFIG_PREEMPT_NONE_BUILD=y
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CONFIG_PTP_1588_CLOCK_OPTIONAL=y
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CONFIG_RANDSTRUCT_NONE=y
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CONFIG_RATIONAL=y
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CONFIG_REALTEK_PHY=y
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CONFIG_REALTEK_PHY_HWMON=y
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CONFIG_REGMAP=y
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CONFIG_REGMAP_MMIO=y
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CONFIG_SCSI=y
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CONFIG_SCSI_COMMON=y
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CONFIG_SERIAL_8250_FSL=y
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CONFIG_SERIAL_MCTRL_GPIO=y
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CONFIG_SERIAL_OF_PLATFORM=y
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CONFIG_SG_POOL=y
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CONFIG_SOFTIRQ_ON_OWN_STACK=y
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CONFIG_SPARSE_IRQ=y
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CONFIG_SPLIT_PTLOCK_CPUS=999999
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CONFIG_SWPHY=y
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CONFIG_SYS_SUPPORTS_APM_EMULATION=y
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CONFIG_THREAD_INFO_IN_TASK=y
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CONFIG_TICK_CPU_ACCOUNTING=y
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CONFIG_TIMER_OF=y
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CONFIG_TIMER_PROBE=y
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CONFIG_TINY_SRCU=y
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CONFIG_UNCOMPRESS_INCLUDE="debug/uncompress.h"
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CONFIG_UNWINDER_ARM=y
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CONFIG_USB=y
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CONFIG_USB_COMMON=y
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CONFIG_USB_EHCI_BIG_ENDIAN_DESC=y
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CONFIG_USB_EHCI_BIG_ENDIAN_MMIO=y
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CONFIG_USB_EHCI_HCD=y
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CONFIG_USB_EHCI_HCD_PLATFORM=y
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CONFIG_USB_EHCI_PCI=y
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CONFIG_USB_OHCI_HCD=y
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CONFIG_USB_OHCI_HCD_PCI=y
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# CONFIG_USB_OHCI_HCD_PLATFORM is not set
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CONFIG_USB_PCI=y
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CONFIG_USB_STORAGE=y
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CONFIG_USB_SUPPORT=y
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CONFIG_USB_UHCI_HCD=y
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CONFIG_USE_OF=y
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CONFIG_VM_EVENT_COUNTERS=y
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CONFIG_WAN=y
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CONFIG_WATCHDOG_CORE=y
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CONFIG_WATCHDOG_NOWAYOUT=y
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CONFIG_XZ_DEC_ARM=y
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CONFIG_XZ_DEC_BCJ=y
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CONFIG_ZBOOT_ROM_BSS=0x0
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CONFIG_ZBOOT_ROM_TEXT=0x0
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@ -1,41 +0,0 @@
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From eff2700d2ec99aac06fff0ad35cbc594bd3e04a8 Mon Sep 17 00:00:00 2001
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From: Linus Walleij <linus.walleij@linaro.org>
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Date: Mon, 10 Feb 2025 10:31:16 +0100
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Subject: [PATCH 1/2] ARM: dts: ixp4xx: Fix up PCI on WG302
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Looking at the board file for WG302 v2 was not a good idea
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because the GPIO IRQ for slot 2 differs, and v1 uses GPIO
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10 instead of GPIO 9. Fix it up.
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Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
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Link: https://lore.kernel.org/20250210-ixp4xx-dts-v1-2-6b752d745e04@linaro.org
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---
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.../dts/intel/ixp/intel-ixp42x-netgear-wg302v1.dts | 10 +++++-----
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1 file changed, 5 insertions(+), 5 deletions(-)
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--- a/arch/arm/boot/dts/intel/ixp/intel-ixp42x-netgear-wg302v1.dts
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+++ b/arch/arm/boot/dts/intel/ixp/intel-ixp42x-netgear-wg302v1.dts
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@@ -57,7 +57,7 @@
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status = "okay";
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/*
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- * Taken from WG302 v2 PCI boardfile (wg302v2-pci.c)
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+ * Taken from WG302 v1 PCI boardfile (wg302v1-pci.c)
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* We have slots (IDSEL) 1 and 2 with one assigned IRQ
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* each handling all IRQs.
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*/
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@@ -70,10 +70,10 @@
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<0x0800 0 0 3 &gpio0 8 IRQ_TYPE_LEVEL_LOW>, /* INT C on slot 1 is irq 8 */
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<0x0800 0 0 4 &gpio0 8 IRQ_TYPE_LEVEL_LOW>, /* INT D on slot 1 is irq 8 */
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/* IDSEL 2 */
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- <0x1000 0 0 1 &gpio0 9 IRQ_TYPE_LEVEL_LOW>, /* INT A on slot 2 is irq 9 */
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- <0x1000 0 0 2 &gpio0 9 IRQ_TYPE_LEVEL_LOW>, /* INT B on slot 2 is irq 9 */
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- <0x1000 0 0 3 &gpio0 9 IRQ_TYPE_LEVEL_LOW>, /* INT C on slot 2 is irq 9 */
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- <0x1000 0 0 4 &gpio0 9 IRQ_TYPE_LEVEL_LOW>; /* INT D on slot 2 is irq 9 */
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+ <0x1000 0 0 1 &gpio0 10 IRQ_TYPE_LEVEL_LOW>, /* INT A on slot 2 is irq 10 */
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+ <0x1000 0 0 2 &gpio0 10 IRQ_TYPE_LEVEL_LOW>, /* INT B on slot 2 is irq 10 */
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+ <0x1000 0 0 3 &gpio0 10 IRQ_TYPE_LEVEL_LOW>, /* INT C on slot 2 is irq 10 */
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+ <0x1000 0 0 4 &gpio0 10 IRQ_TYPE_LEVEL_LOW>; /* INT D on slot 2 is irq 10 */
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};
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ethernet@c8009000 {
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@ -1,60 +0,0 @@
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From f8a9ef38de91ddffa51255d15589c460bb6d9916 Mon Sep 17 00:00:00 2001
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From: Linus Walleij <linus.walleij@linaro.org>
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Date: Mon, 10 Feb 2025 10:31:17 +0100
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Subject: [PATCH 2/2] ARM: dts: ixp4xx: Add Netgear WG302 v1 GPIOs
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This adds GPIO LED indicators, the reset GPIO RESET
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button on the Netgear WG302 v1 to the device tree.
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Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
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Link: https://lore.kernel.org/20250210-ixp4xx-dts-v1-3-6b752d745e04@linaro.org
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---
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.../ixp/intel-ixp42x-netgear-wg302v1.dts | 30 +++++++++++++++++++
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1 file changed, 30 insertions(+)
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--- a/arch/arm/boot/dts/intel/ixp/intel-ixp42x-netgear-wg302v1.dts
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+++ b/arch/arm/boot/dts/intel/ixp/intel-ixp42x-netgear-wg302v1.dts
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@@ -8,6 +8,7 @@
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#include "intel-ixp42x.dtsi"
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#include <dt-bindings/input/input.h>
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+#include <dt-bindings/leds/common.h>
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|
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/ {
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model = "Netgear WG302 v1";
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@@ -32,6 +33,35 @@
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serial0 = &uart1;
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};
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+ leds {
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+ compatible = "gpio-leds";
|
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+ test_led: led-test {
|
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+ color = <LED_COLOR_ID_AMBER>;
|
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+ function = "test";
|
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+ gpios = <&gpio0 4 GPIO_ACTIVE_LOW>;
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+ default-state = "off";
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+ };
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||||
+ wlan_led: led-wlan {
|
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+ color = <LED_COLOR_ID_GREEN>;
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+ function = LED_FUNCTION_WLAN;
|
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+ gpios = <&gpio0 5 GPIO_ACTIVE_LOW>;
|
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+ default-state = "off";
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+ linux,default-trigger = "phy0tx";
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+ };
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+ };
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+
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+ gpio_keys {
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+ /* RESET is on GPIO13 which can't fire interrupts */
|
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+ compatible = "gpio-keys-polled";
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+ poll-interval = <100>;
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+
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+ button-reset {
|
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+ linux,code = <KEY_RESTART>;
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+ label = "reset";
|
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+ gpios = <&gpio0 13 GPIO_ACTIVE_LOW>;
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+ };
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||||
+ };
|
||||
+
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soc {
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bus@c4000000 {
|
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flash@0,0 {
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||||
@ -1,26 +0,0 @@
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From 38623d532c99ebd926f4eebb7c7de19cb7e5aef4 Mon Sep 17 00:00:00 2001
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From: Linus Walleij <linus.walleij@linaro.org>
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Date: Fri, 22 Aug 2025 17:46:28 +0200
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Subject: [PATCH] gpio: mmio: Add compatible for the ixp4xx eb MMIO
|
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|
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The IXP4xx expansion bus can have simple memory-mapped GPIO
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on it. Using the proper device tree bindings, support probing
|
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this directly from the device tree.
|
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|
||||
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
|
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Link: https://lore.kernel.org/r/20250822-ixp4xx-eb-mmio-gpio-v2-3-bd2edd4a9c74@linaro.org
|
||||
Signed-off-by: Bartosz Golaszewski <bartosz.golaszewski@linaro.org>
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||||
---
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drivers/gpio/gpio-mmio.c | 1 +
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1 file changed, 1 insertion(+)
|
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--- a/drivers/gpio/gpio-mmio.c
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+++ b/drivers/gpio/gpio-mmio.c
|
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@@ -687,6 +687,7 @@ static const struct of_device_id bgpio_o
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{ .compatible = "brcm,bcm6345-gpio" },
|
||||
{ .compatible = "wd,mbl-gpio" },
|
||||
{ .compatible = "ni,169445-nand-gpio" },
|
||||
+ { .compatible = "intel,ixp4xx-expansion-bus-mmio-gpio" },
|
||||
{ }
|
||||
};
|
||||
MODULE_DEVICE_TABLE(of, bgpio_of_match);
|
||||
@ -1,156 +0,0 @@
|
||||
From c9cc6b6a7d23eea7ada69a9185a550c4f0b62319 Mon Sep 17 00:00:00 2001
|
||||
From: Linus Walleij <linus.walleij@linaro.org>
|
||||
Date: Wed, 25 Jun 2025 08:51:25 +0200
|
||||
Subject: [PATCH] ARM: dts: Fix up wrv54g device tree
|
||||
|
||||
Fix up the KS8995 switch and PHYs the way that is most likely:
|
||||
|
||||
- Phy 1-4 is certainly the PHYs of the KS8995 (mask 0x1e in
|
||||
the outoftree code masks PHYs 1,2,3,4).
|
||||
- Phy 5 is the MII-P5 separate WAN phy of the KS8995 directly
|
||||
connected to EthC.
|
||||
- The EthB MII is probably connected as CPU interface to the
|
||||
KS8995.
|
||||
|
||||
Properly integrate the KS8995 switch using the new bindings.
|
||||
|
||||
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
|
||||
Reviewed-by: Andrew Lunn <andrew@lunn.ch>
|
||||
Link: https://patch.msgid.link/20250625-ks8995-dsa-bindings-v2-2-ce71dce9be0b@linaro.org
|
||||
Signed-off-by: Jakub Kicinski <kuba@kernel.org>
|
||||
---
|
||||
.../intel/ixp/intel-ixp42x-linksys-wrv54g.dts | 92 ++++++++++++++++---
|
||||
1 file changed, 78 insertions(+), 14 deletions(-)
|
||||
|
||||
--- a/arch/arm/boot/dts/intel/ixp/intel-ixp42x-linksys-wrv54g.dts
|
||||
+++ b/arch/arm/boot/dts/intel/ixp/intel-ixp42x-linksys-wrv54g.dts
|
||||
@@ -72,10 +72,55 @@
|
||||
cs-gpios = <&gpio0 5 GPIO_ACTIVE_LOW>;
|
||||
num-chipselects = <1>;
|
||||
|
||||
- switch@0 {
|
||||
+ ethernet-switch@0 {
|
||||
compatible = "micrel,ks8995";
|
||||
reg = <0>;
|
||||
spi-max-frequency = <50000000>;
|
||||
+
|
||||
+ /*
|
||||
+ * The PHYs are accessed over the external MDIO
|
||||
+ * bus and not internally through the switch control
|
||||
+ * registers.
|
||||
+ */
|
||||
+ ethernet-ports {
|
||||
+ #address-cells = <1>;
|
||||
+ #size-cells = <0>;
|
||||
+
|
||||
+ ethernet-port@0 {
|
||||
+ reg = <0>;
|
||||
+ label = "1";
|
||||
+ phy-mode = "mii";
|
||||
+ phy-handle = <&phy1>;
|
||||
+ };
|
||||
+ ethernet-port@1 {
|
||||
+ reg = <1>;
|
||||
+ label = "2";
|
||||
+ phy-mode = "mii";
|
||||
+ phy-handle = <&phy2>;
|
||||
+ };
|
||||
+ ethernet-port@2 {
|
||||
+ reg = <2>;
|
||||
+ label = "3";
|
||||
+ phy-mode = "mii";
|
||||
+ phy-handle = <&phy3>;
|
||||
+ };
|
||||
+ ethernet-port@3 {
|
||||
+ reg = <3>;
|
||||
+ label = "4";
|
||||
+ phy-mode = "mii";
|
||||
+ phy-handle = <&phy4>;
|
||||
+ };
|
||||
+ ethernet-port@4 {
|
||||
+ reg = <4>;
|
||||
+ ethernet = <ðb>;
|
||||
+ phy-mode = "mii";
|
||||
+ fixed-link {
|
||||
+ speed = <100>;
|
||||
+ full-duplex;
|
||||
+ };
|
||||
+ };
|
||||
+
|
||||
+ };
|
||||
};
|
||||
};
|
||||
|
||||
@@ -135,40 +180,59 @@
|
||||
};
|
||||
|
||||
/*
|
||||
- * EthB - connected to the KS8995 switch ports 1-4
|
||||
- * FIXME: the boardfile defines .phy_mask = 0x1e for this port to enable output to
|
||||
- * all four switch ports, also using an out of tree multiphy patch.
|
||||
- * Do we need a new binding and property for this?
|
||||
+ * EthB connects to the KS8995 CPU port and faces ports 1-4
|
||||
+ * through the switch fabric.
|
||||
+ *
|
||||
+ * To complicate things, the MDIO channel is also only
|
||||
+ * accessible through EthB, but used independently for PHY
|
||||
+ * control.
|
||||
*/
|
||||
- ethernet@c8009000 {
|
||||
+ ethb: ethernet@c8009000 {
|
||||
status = "okay";
|
||||
queue-rx = <&qmgr 3>;
|
||||
queue-txready = <&qmgr 20>;
|
||||
- phy-mode = "rgmii";
|
||||
- phy-handle = <&phy4>;
|
||||
+ phy-mode = "mii";
|
||||
+ fixed-link {
|
||||
+ speed = <100>;
|
||||
+ full-duplex;
|
||||
+ };
|
||||
|
||||
mdio {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
|
||||
- /* Should be ports 1-4 on the KS8995 switch */
|
||||
+ /*
|
||||
+ * LAN ports 1-4 on the KS8995 switch
|
||||
+ * and PHY5 for WAN need to be accessed
|
||||
+ * through this external MDIO channel.
|
||||
+ */
|
||||
+ phy1: ethernet-phy@1 {
|
||||
+ reg = <1>;
|
||||
+ };
|
||||
+ phy2: ethernet-phy@2 {
|
||||
+ reg = <2>;
|
||||
+ };
|
||||
+ phy3: ethernet-phy@3 {
|
||||
+ reg = <3>;
|
||||
+ };
|
||||
phy4: ethernet-phy@4 {
|
||||
reg = <4>;
|
||||
};
|
||||
-
|
||||
- /* Should be port 5 on the KS8995 switch */
|
||||
phy5: ethernet-phy@5 {
|
||||
reg = <5>;
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
- /* EthC - connected to KS8995 switch port 5 */
|
||||
- ethernet@c800a000 {
|
||||
+ /*
|
||||
+ * EthC connects to MII-P5 on the KS8995 bypassing
|
||||
+ * all of the switch logic and facing PHY5
|
||||
+ */
|
||||
+ ethc: ethernet@c800a000 {
|
||||
status = "okay";
|
||||
queue-rx = <&qmgr 4>;
|
||||
queue-txready = <&qmgr 21>;
|
||||
- phy-mode = "rgmii";
|
||||
+ phy-mode = "mii";
|
||||
phy-handle = <&phy5>;
|
||||
};
|
||||
};
|
||||
@ -1,391 +0,0 @@
|
||||
From 85ac6b806993200fe117f4fd047c74784ec6b515 Mon Sep 17 00:00:00 2001
|
||||
From: Linus Walleij <linus.walleij@linaro.org>
|
||||
Date: Fri, 22 Aug 2025 19:56:16 +0200
|
||||
Subject: [PATCH] ARM: dts: Add ixp4xx Actiontec MI424WR device trees
|
||||
|
||||
The Actiontex MI424WR is a pretty widespread home router, made
|
||||
in many different revisions.
|
||||
|
||||
Revisions A, C and D are based on IXP42x. We add a device tree
|
||||
for the A/C variant and one for the D variant as these differ in
|
||||
the location of the WAN PHY on the MDIO bus, and the ethernet
|
||||
interfaces for the WAN PHY and the DSA switch are switched around.
|
||||
|
||||
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
|
||||
Link: https://lore.kernel.org/20250822-ixp4xx-mi424wr-dts-v2-3-cc804884474d@linaro.org
|
||||
---
|
||||
arch/arm/boot/dts/intel/ixp/Makefile | 2 +
|
||||
.../ixp/intel-ixp42x-actiontec-mi424wr-ac.dts | 37 +++
|
||||
.../ixp/intel-ixp42x-actiontec-mi424wr-d.dts | 38 +++
|
||||
.../ixp/intel-ixp42x-actiontec-mi424wr.dtsi | 272 ++++++++++++++++++
|
||||
4 files changed, 349 insertions(+)
|
||||
create mode 100644 arch/arm/boot/dts/intel/ixp/intel-ixp42x-actiontec-mi424wr-ac.dts
|
||||
create mode 100644 arch/arm/boot/dts/intel/ixp/intel-ixp42x-actiontec-mi424wr-d.dts
|
||||
create mode 100644 arch/arm/boot/dts/intel/ixp/intel-ixp42x-actiontec-mi424wr.dtsi
|
||||
|
||||
--- a/arch/arm/boot/dts/intel/ixp/Makefile
|
||||
+++ b/arch/arm/boot/dts/intel/ixp/Makefile
|
||||
@@ -1,5 +1,7 @@
|
||||
# SPDX-License-Identifier: GPL-2.0
|
||||
dtb-$(CONFIG_ARCH_IXP4XX) += \
|
||||
+ intel-ixp42x-actiontec-mi424wr-ac.dtb \
|
||||
+ intel-ixp42x-actiontec-mi424wr-d.dtb \
|
||||
intel-ixp42x-linksys-nslu2.dtb \
|
||||
intel-ixp42x-linksys-wrv54g.dtb \
|
||||
intel-ixp42x-freecom-fsg-3.dtb \
|
||||
--- /dev/null
|
||||
+++ b/arch/arm/boot/dts/intel/ixp/intel-ixp42x-actiontec-mi424wr-ac.dts
|
||||
@@ -0,0 +1,37 @@
|
||||
+// SPDX-License-Identifier: ISC
|
||||
+/*
|
||||
+ * Device Tree file for the IXP425-based Actiontec MI424WR revision A and C
|
||||
+ * Based on a board file from OpenWrt by Jose Vasconcellos.
|
||||
+ */
|
||||
+
|
||||
+/dts-v1/;
|
||||
+
|
||||
+#include "intel-ixp42x-actiontec-mi424wr.dtsi"
|
||||
+
|
||||
+/ {
|
||||
+ model = "Actiontec MI424WR rev A/C";
|
||||
+ compatible = "actiontec,mi424wr-ac", "intel,ixp42x";
|
||||
+
|
||||
+ soc {
|
||||
+ /* EthB used for WAN */
|
||||
+ ethernet@c8009000 {
|
||||
+ phy-handle = <&phy17>; // 17 on revision A-C
|
||||
+
|
||||
+ mdio {
|
||||
+ phy17: ethernet-phy@17 {
|
||||
+ /* WAN */
|
||||
+ reg = <17>;
|
||||
+ };
|
||||
+ };
|
||||
+ };
|
||||
+
|
||||
+ /* EthC used for LAN */
|
||||
+ ethernet@c800a000 {
|
||||
+ /* Fixed link to the CPU MII port on the KS8995 */
|
||||
+ fixed-link {
|
||||
+ speed = <100>;
|
||||
+ full-duplex;
|
||||
+ };
|
||||
+ };
|
||||
+ };
|
||||
+};
|
||||
--- /dev/null
|
||||
+++ b/arch/arm/boot/dts/intel/ixp/intel-ixp42x-actiontec-mi424wr-d.dts
|
||||
@@ -0,0 +1,38 @@
|
||||
+// SPDX-License-Identifier: ISC
|
||||
+/*
|
||||
+ * Device Tree file for the IXP425-based Actiontec MI424WR revision D
|
||||
+ * Based on a board file from OpenWrt by Jose Vasconcellos.
|
||||
+ */
|
||||
+
|
||||
+/dts-v1/;
|
||||
+
|
||||
+#include "intel-ixp42x-actiontec-mi424wr.dtsi"
|
||||
+
|
||||
+/ {
|
||||
+ model = "Actiontec MI424WR rev D";
|
||||
+ compatible = "actiontec,mi424wr-d", "intel,ixp42x";
|
||||
+
|
||||
+ soc {
|
||||
+ /* EthB used for LAN */
|
||||
+ ethernet@c8009000 {
|
||||
+ /* Fixed link to the CPU MII port on the KS8995 */
|
||||
+ fixed-link {
|
||||
+ speed = <100>;
|
||||
+ full-duplex;
|
||||
+ };
|
||||
+
|
||||
+ mdio {
|
||||
+ /* PHY ID 0x00221450 */
|
||||
+ phy5: ethernet-phy@5 {
|
||||
+ /* WAN */
|
||||
+ reg = <5>;
|
||||
+ };
|
||||
+ };
|
||||
+ };
|
||||
+
|
||||
+ /* EthC used for WAN */
|
||||
+ ethernet@c800a000 {
|
||||
+ phy-handle = <&phy5>; // 5 on revision D
|
||||
+ };
|
||||
+ };
|
||||
+};
|
||||
--- /dev/null
|
||||
+++ b/arch/arm/boot/dts/intel/ixp/intel-ixp42x-actiontec-mi424wr.dtsi
|
||||
@@ -0,0 +1,272 @@
|
||||
+// SPDX-License-Identifier: ISC
|
||||
+/*
|
||||
+ * Device Tree file for the IXP425-based Actiontec MI424WR
|
||||
+ * Based on a board file from OpenWrt by Jose Vasconcellos.
|
||||
+ */
|
||||
+
|
||||
+#include "intel-ixp42x.dtsi"
|
||||
+#include <dt-bindings/input/input.h>
|
||||
+#include <dt-bindings/leds/common.h>
|
||||
+
|
||||
+/ {
|
||||
+ #address-cells = <1>;
|
||||
+ #size-cells = <1>;
|
||||
+
|
||||
+ memory@0 {
|
||||
+ device_type = "memory";
|
||||
+ reg = <0x00000000 0x02000000>;
|
||||
+ };
|
||||
+
|
||||
+ chosen {
|
||||
+ bootargs = "console=ttyS0,115200n8";
|
||||
+ stdout-path = "uart1:115200n8";
|
||||
+ };
|
||||
+
|
||||
+ leds {
|
||||
+ compatible = "gpio-leds";
|
||||
+
|
||||
+ led-wan-coax {
|
||||
+ color = <LED_COLOR_ID_GREEN>;
|
||||
+ function = "wan-coax";
|
||||
+ gpios = <&gpio0 11 GPIO_ACTIVE_HIGH>;
|
||||
+ default-state = "off";
|
||||
+ };
|
||||
+ led-power-alarm {
|
||||
+ color = <LED_COLOR_ID_RED>;
|
||||
+ function = LED_FUNCTION_ALARM;
|
||||
+ gpios = <&gpio1 0 GPIO_ACTIVE_HIGH>;
|
||||
+ default-state = "off";
|
||||
+ };
|
||||
+ led-power {
|
||||
+ color = <LED_COLOR_ID_GREEN>;
|
||||
+ function = LED_FUNCTION_POWER;
|
||||
+ gpios = <&gpio1 1 GPIO_ACTIVE_HIGH>;
|
||||
+ default-state = "on";
|
||||
+ linux,default-trigger = "heartbeat";
|
||||
+ };
|
||||
+ led-wireless {
|
||||
+ color = <LED_COLOR_ID_GREEN>;
|
||||
+ function = LED_FUNCTION_WLAN;
|
||||
+ gpios = <&gpio1 2 GPIO_ACTIVE_LOW>;
|
||||
+ default-state = "off";
|
||||
+ };
|
||||
+ led-internet-down {
|
||||
+ color = <LED_COLOR_ID_RED>;
|
||||
+ function = "internet-down";
|
||||
+ gpios = <&gpio1 3 GPIO_ACTIVE_HIGH>;
|
||||
+ default-state = "off";
|
||||
+ };
|
||||
+ led-internet-up {
|
||||
+ color = <LED_COLOR_ID_GREEN>;
|
||||
+ function = "internet-up";
|
||||
+ gpios = <&gpio1 4 GPIO_ACTIVE_HIGH>;
|
||||
+ default-state = "off";
|
||||
+ };
|
||||
+ led-lan-coax {
|
||||
+ color = <LED_COLOR_ID_GREEN>;
|
||||
+ function = "lan-coax";
|
||||
+ gpios = <&gpio1 5 GPIO_ACTIVE_HIGH>;
|
||||
+ default-state = "off";
|
||||
+ };
|
||||
+ led-wan-ethernet-alarm {
|
||||
+ color = <LED_COLOR_ID_RED>;
|
||||
+ function = "wan-ethernet-alarm";
|
||||
+ gpios = <&gpio1 6 GPIO_ACTIVE_HIGH>;
|
||||
+ default-state = "off";
|
||||
+ };
|
||||
+ /* The last three LEDs are not mounted but traces exist on the PCB */
|
||||
+ led-phone-1 {
|
||||
+ color = <LED_COLOR_ID_GREEN>;
|
||||
+ function = "phone-1";
|
||||
+ gpios = <&gpio1 8 GPIO_ACTIVE_LOW>;
|
||||
+ default-state = "off";
|
||||
+ };
|
||||
+ led-phone-2 {
|
||||
+ color = <LED_COLOR_ID_GREEN>;
|
||||
+ function = "phone-2";
|
||||
+ gpios = <&gpio1 9 GPIO_ACTIVE_LOW>;
|
||||
+ default-state = "off";
|
||||
+ };
|
||||
+ led-voip {
|
||||
+ color = <LED_COLOR_ID_GREEN>;
|
||||
+ function = "voip";
|
||||
+ gpios = <&gpio1 10 GPIO_ACTIVE_LOW>;
|
||||
+ default-state = "off";
|
||||
+ };
|
||||
+ };
|
||||
+
|
||||
+ gpio_keys {
|
||||
+ compatible = "gpio-keys";
|
||||
+
|
||||
+ button-reset {
|
||||
+ wakeup-source;
|
||||
+ linux,code = <KEY_RESTART>;
|
||||
+ label = "reset";
|
||||
+ gpios = <&gpio0 10 GPIO_ACTIVE_LOW>;
|
||||
+ };
|
||||
+ };
|
||||
+
|
||||
+ spi {
|
||||
+ compatible = "spi-gpio";
|
||||
+ #address-cells = <1>;
|
||||
+ #size-cells = <0>;
|
||||
+
|
||||
+ sck-gpios = <&gpio0 2 GPIO_ACTIVE_HIGH>;
|
||||
+ mosi-gpios = <&gpio0 4 GPIO_ACTIVE_HIGH>;
|
||||
+ miso-gpios = <&gpio0 3 GPIO_ACTIVE_HIGH>;
|
||||
+ cs-gpios = <&gpio0 9 GPIO_ACTIVE_LOW>;
|
||||
+ num-chipselects = <1>;
|
||||
+
|
||||
+ ethernet-switch@0 {
|
||||
+ compatible = "micrel,ks8995";
|
||||
+ reg = <0>;
|
||||
+ spi-max-frequency = <50000000>;
|
||||
+
|
||||
+ ethernet-ports {
|
||||
+ #address-cells = <1>;
|
||||
+ #size-cells = <0>;
|
||||
+
|
||||
+ ethernet-port@0 {
|
||||
+ reg = <0>;
|
||||
+ label = "lan1";
|
||||
+ phy-mode = "mii";
|
||||
+ phy-handle = <&phy1>;
|
||||
+ };
|
||||
+ ethernet-port@1 {
|
||||
+ reg = <1>;
|
||||
+ label = "lan2";
|
||||
+ phy-mode = "mii";
|
||||
+ phy-handle = <&phy2>;
|
||||
+ };
|
||||
+ ethernet-port@2 {
|
||||
+ reg = <2>;
|
||||
+ label = "lan3";
|
||||
+ phy-mode = "mii";
|
||||
+ phy-handle = <&phy3>;
|
||||
+ };
|
||||
+ ethernet-port@3 {
|
||||
+ reg = <3>;
|
||||
+ label = "lan4";
|
||||
+ phy-mode = "mii";
|
||||
+ phy-handle = <&phy4>;
|
||||
+ };
|
||||
+ ethernet-port@4 {
|
||||
+ reg = <4>;
|
||||
+ ethernet = <ðc>;
|
||||
+ phy-mode = "mii";
|
||||
+ fixed-link {
|
||||
+ speed = <100>;
|
||||
+ full-duplex;
|
||||
+ };
|
||||
+ };
|
||||
+
|
||||
+ };
|
||||
+ };
|
||||
+ };
|
||||
+
|
||||
+ soc {
|
||||
+ bus@c4000000 {
|
||||
+ flash@0,0 {
|
||||
+ compatible = "intel,ixp4xx-flash", "cfi-flash";
|
||||
+ bank-width = <2>;
|
||||
+ /*
|
||||
+ * 8 MB of Flash in 64 0x20000 sized blocks
|
||||
+ * mapped in at CS0.
|
||||
+ */
|
||||
+ reg = <0 0x00000000 0x0800000>;
|
||||
+
|
||||
+ /* Configure expansion bus to allow writes */
|
||||
+ intel,ixp4xx-eb-write-enable = <1>;
|
||||
+
|
||||
+ partitions {
|
||||
+ compatible = "redboot-fis";
|
||||
+ fis-index-block = <0x3f>;
|
||||
+ };
|
||||
+ };
|
||||
+ gpio1: gpio@1,0 {
|
||||
+ /* MMIO GPIO at CS1 */
|
||||
+ compatible = "intel,ixp4xx-expansion-bus-mmio-gpio";
|
||||
+ gpio-controller;
|
||||
+ #gpio-cells = <2>;
|
||||
+ big-endian;
|
||||
+ reg = <1 0x00000000 0x2>;
|
||||
+ reg-names = "dat";
|
||||
+ /* Expansion bus settings */
|
||||
+ intel,ixp4xx-eb-write-enable = <1>;
|
||||
+
|
||||
+ pci-reset-hog {
|
||||
+ gpio-hog;
|
||||
+ gpios = <7 GPIO_ACTIVE_HIGH>;
|
||||
+ output-high;
|
||||
+ line-name = "PCI reset";
|
||||
+ };
|
||||
+ pstn-relay-hog-1 {
|
||||
+ gpio-hog;
|
||||
+ gpios = <11 GPIO_ACTIVE_HIGH>;
|
||||
+ output-low;
|
||||
+ line-name = "PSTN relay control 1";
|
||||
+ };
|
||||
+ pstn-relay-hog-2 {
|
||||
+ gpio-hog;
|
||||
+ gpios = <12 GPIO_ACTIVE_HIGH>;
|
||||
+ output-low;
|
||||
+ line-name = "PSTN relay control 2";
|
||||
+ };
|
||||
+ };
|
||||
+ };
|
||||
+
|
||||
+ pci@c0000000 {
|
||||
+ status = "okay";
|
||||
+
|
||||
+ #interrupt-cells = <1>;
|
||||
+ interrupt-map-mask = <0xf800 0 0 7>;
|
||||
+ interrupt-map =
|
||||
+ /* IDSEL 13 */
|
||||
+ <0x6800 0 0 1 &gpio0 8 IRQ_TYPE_LEVEL_LOW>, /* INT A on slot 13 is irq 8 */
|
||||
+ <0x6800 0 0 2 &gpio0 6 IRQ_TYPE_LEVEL_LOW>, /* INT B on slot 13 is irq 6 */
|
||||
+ /* IDSEL 14 */
|
||||
+ <0x7000 0 0 1 &gpio0 8 IRQ_TYPE_LEVEL_LOW>, /* INT A on slot 14 is irq 7 */
|
||||
+ <0x7000 0 0 2 &gpio0 6 IRQ_TYPE_LEVEL_LOW>, /* INT B on slot 14 is irq 8 */
|
||||
+ /* IDSEL 15 */
|
||||
+ <0x7800 0 0 1 &gpio0 8 IRQ_TYPE_LEVEL_LOW>, /* INT A on slot 15 is irq 6 */
|
||||
+ <0x7800 0 0 2 &gpio0 6 IRQ_TYPE_LEVEL_LOW>; /* INT B on slot 15 is irq 7 */
|
||||
+ };
|
||||
+
|
||||
+ ethb: ethernet@c8009000 {
|
||||
+ status = "okay";
|
||||
+ queue-rx = <&qmgr 3>;
|
||||
+ queue-txready = <&qmgr 20>;
|
||||
+ phy-mode = "mii";
|
||||
+
|
||||
+ mdio {
|
||||
+ #address-cells = <1>;
|
||||
+ #size-cells = <0>;
|
||||
+
|
||||
+ /* 1, 2, 3 and 4 are ports on the KS8995 switch */
|
||||
+ phy1: ethernet-phy@1 {
|
||||
+ /* LAN1 */
|
||||
+ reg = <1>;
|
||||
+ };
|
||||
+ phy2: ethernet-phy@2 {
|
||||
+ /* LAN2 */
|
||||
+ reg = <2>;
|
||||
+ };
|
||||
+ phy3: ethernet-phy@3 {
|
||||
+ /* LAN3 */
|
||||
+ reg = <3>;
|
||||
+ };
|
||||
+ phy4: ethernet-phy@4 {
|
||||
+ /* LAN4 */
|
||||
+ reg = <4>;
|
||||
+ };
|
||||
+ };
|
||||
+ };
|
||||
+
|
||||
+ ethc: ethernet@c800a000 {
|
||||
+ status = "okay";
|
||||
+ queue-rx = <&qmgr 4>;
|
||||
+ queue-txready = <&qmgr 21>;
|
||||
+ phy-mode = "mii";
|
||||
+ };
|
||||
+ };
|
||||
+};
|
||||
@ -1,70 +0,0 @@
|
||||
From ececfba255bf3616301419e47a5c824e04b60ab8 Mon Sep 17 00:00:00 2001
|
||||
From: Linus Walleij <linusw@kernel.org>
|
||||
Date: Thu, 11 Dec 2025 14:05:01 +0100
|
||||
Subject: [PATCH] ARM: dts: ixp4xx: Fix up Actiontec MI424WR DTS files
|
||||
|
||||
The KS8995 switch was unconditionally wired to EthC (eth1)
|
||||
on both MI424WR variants, this is wrong: the D revision has
|
||||
the switch connected to EthB (eth0) so pull this assingment
|
||||
out of the generic MI424WR DTSI file and make it a property
|
||||
of the respective variants instead.
|
||||
|
||||
Signed-off-by: Linus Walleij <linusw@kernel.org>
|
||||
Link: https://patch.msgid.link/20251211-ixp4xx-actiontec-dts-fix-v1-1-97af8e79d474@kernel.org
|
||||
Signed-off-by: Krzysztof Kozlowski <krzk@kernel.org>
|
||||
---
|
||||
.../intel/ixp/intel-ixp42x-actiontec-mi424wr-ac.dts | 11 +++++++++++
|
||||
.../intel/ixp/intel-ixp42x-actiontec-mi424wr-d.dts | 11 +++++++++++
|
||||
.../dts/intel/ixp/intel-ixp42x-actiontec-mi424wr.dtsi | 1 -
|
||||
3 files changed, 22 insertions(+), 1 deletion(-)
|
||||
|
||||
--- a/arch/arm/boot/dts/intel/ixp/intel-ixp42x-actiontec-mi424wr-ac.dts
|
||||
+++ b/arch/arm/boot/dts/intel/ixp/intel-ixp42x-actiontec-mi424wr-ac.dts
|
||||
@@ -12,6 +12,17 @@
|
||||
model = "Actiontec MI424WR rev A/C";
|
||||
compatible = "actiontec,mi424wr-ac", "intel,ixp42x";
|
||||
|
||||
+ /* Connect the switch to EthC */
|
||||
+ spi {
|
||||
+ ethernet-switch@0 {
|
||||
+ ethernet-ports {
|
||||
+ ethernet-port@4 {
|
||||
+ ethernet = <ðc>;
|
||||
+ };
|
||||
+ };
|
||||
+ };
|
||||
+ };
|
||||
+
|
||||
soc {
|
||||
/* EthB used for WAN */
|
||||
ethernet@c8009000 {
|
||||
--- a/arch/arm/boot/dts/intel/ixp/intel-ixp42x-actiontec-mi424wr-d.dts
|
||||
+++ b/arch/arm/boot/dts/intel/ixp/intel-ixp42x-actiontec-mi424wr-d.dts
|
||||
@@ -12,6 +12,17 @@
|
||||
model = "Actiontec MI424WR rev D";
|
||||
compatible = "actiontec,mi424wr-d", "intel,ixp42x";
|
||||
|
||||
+ /* Connect the switch to EthB */
|
||||
+ spi {
|
||||
+ ethernet-switch@0 {
|
||||
+ ethernet-ports {
|
||||
+ ethernet-port@4 {
|
||||
+ ethernet = <ðb>;
|
||||
+ };
|
||||
+ };
|
||||
+ };
|
||||
+ };
|
||||
+
|
||||
soc {
|
||||
/* EthB used for LAN */
|
||||
ethernet@c8009000 {
|
||||
--- a/arch/arm/boot/dts/intel/ixp/intel-ixp42x-actiontec-mi424wr.dtsi
|
||||
+++ b/arch/arm/boot/dts/intel/ixp/intel-ixp42x-actiontec-mi424wr.dtsi
|
||||
@@ -152,7 +152,6 @@
|
||||
};
|
||||
ethernet-port@4 {
|
||||
reg = <4>;
|
||||
- ethernet = <ðc>;
|
||||
phy-mode = "mii";
|
||||
fixed-link {
|
||||
speed = <100>;
|
||||
@ -1,24 +0,0 @@
|
||||
From 6484f966af53447deefcd4b805c201d8624981cb Mon Sep 17 00:00:00 2001
|
||||
From: Linus Walleij <linus.walleij@linaro.org>
|
||||
Date: Mon, 29 May 2023 23:32:44 +0200
|
||||
Subject: [PATCH] ARM: dts: ixp4xx: Boot NSLU2 from harddrive
|
||||
|
||||
This enforces harddrive boot on the NSLU2. The flash is too small
|
||||
to hold any rootfs these days.
|
||||
|
||||
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
|
||||
---
|
||||
arch/arm/boot/dts/intel/ixp/intel-ixp42x-linksys-nslu2.dts | 2 +-
|
||||
1 file changed, 1 insertion(+), 1 deletion(-)
|
||||
|
||||
--- a/arch/arm/boot/dts/intel/ixp/intel-ixp42x-linksys-nslu2.dts
|
||||
+++ b/arch/arm/boot/dts/intel/ixp/intel-ixp42x-linksys-nslu2.dts
|
||||
@@ -21,7 +21,7 @@
|
||||
};
|
||||
|
||||
chosen {
|
||||
- bootargs = "console=ttyS0,115200n8 root=/dev/mtdblock2 rw rootfstype=squashfs,jffs2 rootwait";
|
||||
+ bootargs = "console=ttyS0,115200n8 root=/dev/sda1 rw rootwait";
|
||||
stdout-path = "uart0:115200n8";
|
||||
};
|
||||
|
||||
@ -1,228 +0,0 @@
|
||||
From d672011e10097e5e61659a5d64ac9cb7b7544b60 Mon Sep 17 00:00:00 2001
|
||||
From: Linus Walleij <linus.walleij@linaro.org>
|
||||
Date: Wed, 25 Dec 2024 01:09:20 +0100
|
||||
Subject: [PATCH] ARM: dts: ixp4xx OpenWrt LED aliases
|
||||
|
||||
This outoftree patch adds OpenWrt LED aliases to the DTS files
|
||||
of supported devices.
|
||||
|
||||
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
|
||||
---
|
||||
.../boot/dts/intel/ixp/intel-ixp42x-dlink-dsm-g600.dts | 9 ++++++---
|
||||
.../boot/dts/intel/ixp/intel-ixp42x-freecom-fsg-3.dts | 10 +++++++---
|
||||
.../dts/intel/ixp/intel-ixp42x-gateworks-gw2348.dts | 6 +++++-
|
||||
.../boot/dts/intel/ixp/intel-ixp42x-iomega-nas100d.dts | 9 ++++++---
|
||||
.../boot/dts/intel/ixp/intel-ixp42x-linksys-nslu2.dts | 9 ++++++---
|
||||
.../dts/intel/ixp/intel-ixp42x-netgear-wg302v1.dts | 3 +++
|
||||
.../dts/intel/ixp/intel-ixp42x-usrobotics-usr8200.dts | 5 ++++-
|
||||
.../dts/intel/ixp/intel-ixp43x-gateworks-gw2358.dts | 6 +++++-
|
||||
8 files changed, 42 insertions(+), 15 deletions(-)
|
||||
|
||||
--- a/arch/arm/boot/dts/intel/ixp/intel-ixp42x-dlink-dsm-g600.dts
|
||||
+++ b/arch/arm/boot/dts/intel/ixp/intel-ixp42x-dlink-dsm-g600.dts
|
||||
@@ -31,16 +31,19 @@
|
||||
};
|
||||
|
||||
aliases {
|
||||
+ led-boot = &led_power;
|
||||
+ led-failsafe = &led_power;
|
||||
+ led-running = &led_power;
|
||||
+ led-upgrade = &led_power;
|
||||
serial0 = &uart0;
|
||||
};
|
||||
|
||||
leds {
|
||||
compatible = "gpio-leds";
|
||||
- led-power {
|
||||
+ led_power: led-power {
|
||||
label = "dsmg600:green:power";
|
||||
gpios = <&gpio0 0 GPIO_ACTIVE_HIGH>;
|
||||
default-state = "on";
|
||||
- linux,default-trigger = "heartbeat";
|
||||
};
|
||||
led-wlan {
|
||||
label = "dsmg600:green:wlan";
|
||||
@@ -48,7 +51,7 @@
|
||||
gpios = <&gpio0 14 GPIO_ACTIVE_LOW>;
|
||||
default-state = "on";
|
||||
/* We don't have WLAN trigger in the kernel (yet) */
|
||||
- linux,default-trigger = "netdev";
|
||||
+ linux,default-trigger = "phy0tx";
|
||||
};
|
||||
};
|
||||
|
||||
--- a/arch/arm/boot/dts/intel/ixp/intel-ixp42x-freecom-fsg-3.dts
|
||||
+++ b/arch/arm/boot/dts/intel/ixp/intel-ixp42x-freecom-fsg-3.dts
|
||||
@@ -29,6 +29,10 @@
|
||||
};
|
||||
|
||||
aliases {
|
||||
+ led-boot = &led_ring;
|
||||
+ led-failsafe = &led_sync;
|
||||
+ led-running = &led_ring;
|
||||
+ led-upgrade = &led_sync;
|
||||
serial0 = &uart0;
|
||||
};
|
||||
|
||||
@@ -112,7 +116,7 @@
|
||||
reg = <0x00 0x02>;
|
||||
mask = <0x01>;
|
||||
label = "fsg:blue:wlan";
|
||||
- linux,default-trigger = "wlan";
|
||||
+ linux,default-trigger = "phy0tx";
|
||||
default-state = "on";
|
||||
};
|
||||
led@0,1 {
|
||||
@@ -139,7 +143,7 @@
|
||||
linux,default-trigger = "";
|
||||
default-state = "on";
|
||||
};
|
||||
- led@0,4 {
|
||||
+ led_sync: led@0,4 {
|
||||
compatible = "register-bit-led";
|
||||
reg = <0x00 0x02>;
|
||||
mask = <0x08>;
|
||||
@@ -147,7 +151,7 @@
|
||||
linux,default-trigger = "";
|
||||
default-state = "on";
|
||||
};
|
||||
- led@0,5 {
|
||||
+ led_ring: led@0,5 {
|
||||
compatible = "register-bit-led";
|
||||
reg = <0x00 0x02>;
|
||||
mask = <0x10>;
|
||||
--- a/arch/arm/boot/dts/intel/ixp/intel-ixp42x-gateworks-gw2348.dts
|
||||
+++ b/arch/arm/boot/dts/intel/ixp/intel-ixp42x-gateworks-gw2348.dts
|
||||
@@ -26,12 +26,16 @@
|
||||
};
|
||||
|
||||
aliases {
|
||||
+ led-boot = &usr_led;
|
||||
+ led-failsafe = &usr_led;
|
||||
+ led-running = &usr_led;
|
||||
+ led-upgrade = &usr_led;
|
||||
serial0 = &uart0;
|
||||
};
|
||||
|
||||
leds {
|
||||
compatible = "gpio-leds";
|
||||
- led-user {
|
||||
+ usr_led: led-user {
|
||||
label = "gw2348:green:user";
|
||||
gpios = <&gpio0 3 GPIO_ACTIVE_LOW>;
|
||||
default-state = "on";
|
||||
--- a/arch/arm/boot/dts/intel/ixp/intel-ixp42x-iomega-nas100d.dts
|
||||
+++ b/arch/arm/boot/dts/intel/ixp/intel-ixp42x-iomega-nas100d.dts
|
||||
@@ -26,6 +26,10 @@
|
||||
};
|
||||
|
||||
aliases {
|
||||
+ led-boot = &pwr_led;
|
||||
+ led-failsafe = &pwr_led;
|
||||
+ led-running = &pwr_led;
|
||||
+ led-upgrade = &pwr_led;
|
||||
serial0 = &uart0;
|
||||
};
|
||||
|
||||
@@ -36,7 +40,7 @@
|
||||
gpios = <&gpio0 0 GPIO_ACTIVE_HIGH>;
|
||||
default-state = "on";
|
||||
/* We don't have WLAN trigger in the kernel (yet) */
|
||||
- linux,default-trigger = "netdev";
|
||||
+ linux,default-trigger = "phy0tx";
|
||||
};
|
||||
led-disk {
|
||||
label = "nas100d:red:disk";
|
||||
@@ -44,11 +48,10 @@
|
||||
default-state = "on";
|
||||
linux,default-trigger = "disk-activity";
|
||||
};
|
||||
- led-power {
|
||||
+ pwr_led: led-power {
|
||||
label = "nas100d:red:power";
|
||||
gpios = <&gpio0 15 GPIO_ACTIVE_LOW>;
|
||||
default-state = "on";
|
||||
- linux,default-trigger = "heartbeat";
|
||||
};
|
||||
};
|
||||
|
||||
--- a/arch/arm/boot/dts/intel/ixp/intel-ixp42x-linksys-nslu2.dts
|
||||
+++ b/arch/arm/boot/dts/intel/ixp/intel-ixp42x-linksys-nslu2.dts
|
||||
@@ -26,18 +26,21 @@
|
||||
};
|
||||
|
||||
aliases {
|
||||
+ led-boot = &led_status;
|
||||
+ led-failsafe = &led_status;
|
||||
+ led-running = &led_ready;
|
||||
+ led-upgrade = &led_status;
|
||||
serial0 = &uart0;
|
||||
};
|
||||
|
||||
leds {
|
||||
compatible = "gpio-leds";
|
||||
- led-status {
|
||||
+ led_status: led-status {
|
||||
label = "nslu2:red:status";
|
||||
gpios = <&gpio0 0 GPIO_ACTIVE_HIGH>;
|
||||
default-state = "on";
|
||||
- linux,default-trigger = "heartbeat";
|
||||
};
|
||||
- led-ready {
|
||||
+ led_ready: led-ready {
|
||||
label = "nslu2:green:ready";
|
||||
gpios = <&gpio0 1 GPIO_ACTIVE_HIGH>;
|
||||
default-state = "on";
|
||||
--- a/arch/arm/boot/dts/intel/ixp/intel-ixp42x-netgear-wg302v1.dts
|
||||
+++ b/arch/arm/boot/dts/intel/ixp/intel-ixp42x-netgear-wg302v1.dts
|
||||
@@ -29,6 +29,9 @@
|
||||
};
|
||||
|
||||
aliases {
|
||||
+ led-boot = &test_led;
|
||||
+ led-failsafe = &test_led;
|
||||
+ led-upgrade = &test_led;
|
||||
/* These are switched around */
|
||||
serial0 = &uart1;
|
||||
};
|
||||
--- a/arch/arm/boot/dts/intel/ixp/intel-ixp42x-usrobotics-usr8200.dts
|
||||
+++ b/arch/arm/boot/dts/intel/ixp/intel-ixp42x-usrobotics-usr8200.dts
|
||||
@@ -29,6 +29,10 @@
|
||||
};
|
||||
|
||||
aliases {
|
||||
+ led-boot = &pwr_led;
|
||||
+ led-failsafe = &pwr_led;
|
||||
+ led-running = &pwr_led;
|
||||
+ led-upgrade = &pwr_led;
|
||||
/* These are switched around */
|
||||
serial0 = &uart1;
|
||||
serial1 = &uart0;
|
||||
@@ -67,7 +71,6 @@
|
||||
label = "usr8200:green:pwr";
|
||||
gpios = <&gpio0 14 GPIO_ACTIVE_HIGH>;
|
||||
default-state = "on";
|
||||
- linux,default-trigger = "heartbeat";
|
||||
};
|
||||
};
|
||||
|
||||
--- a/arch/arm/boot/dts/intel/ixp/intel-ixp43x-gateworks-gw2358.dts
|
||||
+++ b/arch/arm/boot/dts/intel/ixp/intel-ixp43x-gateworks-gw2358.dts
|
||||
@@ -25,12 +25,16 @@
|
||||
};
|
||||
|
||||
aliases {
|
||||
+ led-boot = &usr_led;
|
||||
+ led-failsafe = &usr_led;
|
||||
+ led-running = &usr_led;
|
||||
+ led-upgrade = &usr_led;
|
||||
serial0 = &uart0;
|
||||
};
|
||||
|
||||
leds {
|
||||
compatible = "gpio-leds";
|
||||
- led-user {
|
||||
+ usr_led: led-user {
|
||||
label = "gw2358:green:LED";
|
||||
gpios = <&pld1 0 GPIO_ACTIVE_LOW>;
|
||||
default-state = "on";
|
||||
Loading…
Reference in New Issue
Block a user